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PCF8564ACX9/B/1,02

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 19 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
[1] F
0
is clocked at 32.768 kHz.
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP
bit is released. The uncertainty is caused by the prescaler bits F
0
and F
1
not being reset
(see Table 27
) and the unknown state of the 32 kHz clock.
8.11 Reset
The PCF8564A includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I
2
C-bus logic is initialized including the address pointer and
all registers are set according to Table 28
. I
2
C-bus communication is not possible during
reset.
Table 27. First increment of time circuits after STOP bit release
Bit Prescaler bits
[1]
1Hz tick Time Comment
STOP F
0
F
1
-F
2
to F
14
hh:mm:ss
Clock is running normally
0
01-0 0001 1101 0100
12:45:12 prescaler counting normally
STOP bit is activated by user. F
0
F
1
are not reset and values cannot be predicted externally
1
XX-0 0000 0000 0000
12:45:12 prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00 prescaler is reset; time circuits are frozen
STOP bit is released by user
0
XX-0 0000 0000 0000
08:00:00 prescaler is now running
XX-1 0000 0000 0000
08:00:00 -
XX-0 1000 0000 0000
08:00:00 -
XX-1 1000 0000 0000
08:00:00 -
:
::
11-1 1111 1111 1110
08:00:00 -
00-0 0000 0000 0001
08:00:01 0 to 1 transition of F
14
increments the time circuits
10-0 0000 0000 0001
08:00:01 -
:
::
11-1 1111 1111 1111
08:00:01 -
00-0 0000 0000 0000
08:00:01 -
10-0 0000 0000 0000
08:00:01 -
:
:-
11-1 1111 1111 1110
08:00:01 -
00-0 0000 0000 0001
08:00:02 0 to 1 transition of F
14
increments the time circuits
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PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 20 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
[1] Registers marked ‘x’ are undefined at power-on and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a circuit has been implemented to
disable the POR and speed up functional test of the module. The setting of this mode
requires that the I
2
C signals on the pins SDA and SCL are toggled as illustrated in
Figure 10
. All timings shown are required minimums.
Once the override mode has been entered, the chip immediately stops, being reset, and
normal operation may begin, i.e., entry into the EXT_CLK test mode via I
2
C access. The
override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1
before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal
operation has no effect, except to prevent entry into the POR override mode.
Table 28. Register reset values
[1]
Address Register name Bit
7 6 5 4 3 2 1 0
00h Control_1 00001000
01h Control_2 00000000
02hSeconds 1xxxxxxx
03hMinutes xxxxxxxx
04hHours xxxxxxxx
05hDays xxxxxxxx
06hWeekdays xxxxxxxx
07hMonths xxxxxxxx
08hYears xxxxxxxx
09hMinute_alarm 1xxxxxxx
0AhHour_alarm 1xxxxxxx
0BhDay_alarm 1xxxxxxx
0ChWeekday_alarm1xxxxxxx
0DhCLKOUT_ctrl 1xxxxx00
0EhTimer_ctrl 0xxxxx11
0FhTimer xxxxxxxx
Allow 500 ns between the edges of either signal.
Fig 10. POR override sequence
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PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 21 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
9. Characteristics of the I
2
C-bus
The I
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 11
).
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the
STOP condition (P), see Figure 12
.
9.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 13
).
Fig 11. Bit transfer
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Fig 12. Definition of START and STOP conditions
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PCF8564ACX9/B/1,02

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Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR I2C DIE
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