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PCF8564ACX9/B/1,02

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 46 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
25. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 5. Register overview. . . . . . . . . . . . . . . . . . . . . . . .6
Table 6. Control_1 - control and status register 1
(address 00h) bit description . . . . . . . . . . . . . . .7
Table 7. Control_2 - control and status register 2
(address 01h) bit description . . . . . . . . . . . . . . .7
Table 8. INT
operation (bit TI_TP = 1)
[1]
. . . . . . . . . . . . . .8
Table 9. Seconds - seconds and clock integrity status
register (address 02h) bit description . . . . . . . . .9
Table 10. Seconds coded in BCD format . . . . . . . . . . . . .9
Table 11. Minutes - minutes register (address 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 12. Hours - hours register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 13. Days - days register (address 05h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 14. Weekdays - weekdays register
(address 06h) bit description . . . . . . . . . . . . . .10
Table 15. Weekday assignments . . . . . . . . . . . . . . . . . .11
Table 16. Months - months and century flag register
(address 07h) bit description . . . . . . . . . . . . . .11
Table 17. Month assignments coded in BCD format . . .11
Table 18. Years - years register (08h) bit description. . . .12
Table 19. Minute_alarm - minute alarm register
(address 09h) bit description . . . . . . . . . . . . . .13
Table 20. Hour_alarm - hour alarm register
(address 0Ah) bit description . . . . . . . . . . . . . .14
Table 21. Day_alarm - day alarm register
(address 0Bh) bit description . . . . . . . . . . . . . .14
Table 22. Weekday_alarm - weekday alarm register
(address 0Ch) bit description . . . . . . . . . . . . . .14
Table 23. CLKOUT_ctrl - CLKOUT control register
(address 0Dh) bit description . . . . . . . . . . . . . .16
Table 24. Timer_ctrl - timer control register
(address 0Eh) bit description . . . . . . . . . . . . . .16
Table 25. Timer - timer register (address 0Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 26. Timer register bits value range . . . . . . . . . . . . .17
Table 27. First increment of time circuits after STOP
bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 28. Register reset values
[1]
. . . . . . . . . . . . . . . . . .20
Table 29. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 30. Static characteristics . . . . . . . . . . . . . . . . . . . .28
Table 31. Dynamic characteristics . . . . . . . . . . . . . . . . . .31
Table 32. Dimensions of PCF8564AU/x . . . . . . . . . . . . .34
Table 33. Dimensions of PCF8564AUG/x . . . . . . . . . . .36
Table 34. Pin location of all PCF8564A types . . . . . . . .37
Table 35. Alignment marks of all PCF8564A types . . . . .37
Table 36. Gold bump hardness . . . . . . . . . . . . . . . . . . . .37
Table 37. PCF8564A wafer information . . . . . . . . . . . . . .40
Table 38. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 39. Revision history . . . . . . . . . . . . . . . . . . . . . . . .43
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 47 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
26. Figures
Fig 1. Block diagram of PCF8564A . . . . . . . . . . . . . . . . .3
Fig 2. Pinning diagram of PCF8564A . . . . . . . . . . . . . . .4
Fig 3. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8
Fig 4. Voltage low detection. . . . . . . . . . . . . . . . . . . . . . .9
Fig 5. Data flow for the time function . . . . . . . . . . . . . . .12
Fig 6. Access time for read/write operations . . . . . . . . .13
Fig 7. Alarm function block diagram. . . . . . . . . . . . . . . .15
Fig 8. STOP bit functional diagram . . . . . . . . . . . . . . . .18
Fig 9. STOP bit release timing. . . . . . . . . . . . . . . . . . . .18
Fig 10. POR override sequence . . . . . . . . . . . . . . . . . . .20
Fig 11. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fig 12. Definition of START and STOP conditions. . . . . .21
Fig 13. System configuration . . . . . . . . . . . . . . . . . . . . . .22
Fig 14. Acknowledgment on the I
2
C-bus . . . . . . . . . . . . .22
Fig 15. Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 16. Master transmits to slave receiver
(WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 17. Master reads word after setting word address
(write word address; READ data) . . . . . . . . . . . .24
Fig 18. Master reads slave immediately after first byte
(READ mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Fig 19. Interface watchdog timer . . . . . . . . . . . . . . . . . . .25
Fig 20. Device diode protection diagram . . . . . . . . . . . . .26
Fig 21. I
DD
as a function of V
DD
. . . . . . . . . . . . . . . . . . . .30
Fig 22. I
DD
as a function of V
DD
. . . . . . . . . . . . . . . . . . . .30
Fig 23. I
DD
as a function of temperature . . . . . . . . . . . . .30
Fig 24. Frequency deviation as a function of V
DD
. . . . . .30
Fig 25. I
2
C-bus timing waveforms . . . . . . . . . . . . . . . . . .32
Fig 26. Application diagram . . . . . . . . . . . . . . . . . . . . . . .32
Fig 27. Bare die outline of PCF8564AU/x . . . . . . . . . . . .33
Fig 28. Bare die outline of PCF8564AUG/x. . . . . . . . . . .35
Fig 29. Alignment marks of all PCF8564A types . . . . . . .37
Fig 30. Wafer layout of PCF8564A . . . . . . . . . . . . . . . . .39
Fig 31. Film Frame Carrier (FFC) for 6 inch wafer
(PCF8564AU/10AB/1) . . . . . . . . . . . . . . . . . . . . .40
Fig 32. Film Frame Carrier (FFC) for 8 inch wafer
(PCF8564AUG/12HB/1) . . . . . . . . . . . . . . . . . . .41
NXP Semiconductors
PCF8564A
Real time clock and calendar
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 August 2013
Document identifier: PCF8564A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
27. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Functional description . . . . . . . . . . . . . . . . . . . 5
8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5
8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6
8.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7
8.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7
8.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 7
8.3.2.1 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8
8.4 Time and date registers . . . . . . . . . . . . . . . . . . 9
8.4.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . . 9
8.4.1.1 Voltage low detector and clock monitor . . . . . . 9
8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10
8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10
8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10
8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 10
8.4.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 11
8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12
8.5 Setting and reading the time. . . . . . . . . . . . . . 12
8.6 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13
8.6.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 13
8.6.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14
8.6.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14
8.6.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 14
8.6.5 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.7 Register CLKOUT_ctrl and clock output. . . . . 15
8.8 Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16
8.8.1 Register Timer_ctrl . . . . . . . . . . . . . . . . . . . . . 16
8.8.2 Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17
8.9 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17
8.9.1 Operation example . . . . . . . . . . . . . . . . . . . . . 17
8.10 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18
8.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.11.1 Power-On Reset (POR) override . . . . . . . . . . 20
9 Characteristics of the I
2
C-bus . . . . . . . . . . . . 21
9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2 START and STOP conditions . . . . . . . . . . . . . 21
9.3 System configuration . . . . . . . . . . . . . . . . . . . 21
9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 I
2
C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23
10.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10.2 Clock and calendar READ or WRITE cycles . 23
10.3 Interface watchdog timer . . . . . . . . . . . . . . . . 25
11 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26
12 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27
14 Static characteristics . . . . . . . . . . . . . . . . . . . 28
15 Dynamic characteristics. . . . . . . . . . . . . . . . . 31
16 Application information . . . . . . . . . . . . . . . . . 32
17 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 33
18 Handling information . . . . . . . . . . . . . . . . . . . 38
19 Packing information . . . . . . . . . . . . . . . . . . . . 39
19.1 Wafer and Film Frame Carrier
(FFC) information. . . . . . . . . . . . . . . . . . . . . . 39
20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42
21 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
23 Legal information . . . . . . . . . . . . . . . . . . . . . . 44
23.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 44
23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
23.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
24 Contact information . . . . . . . . . . . . . . . . . . . . 45
25 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
26 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PCF8564ACX9/B/1,02

Mfr. #:
Buy PCF8564ACX9/B/1,02
Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR I2C DIE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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