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CS1600-FSZ

P1-P3P4-P6P7-P9P10-P12P13-P14
CS1600
DS904F1 7
Frequency (kHz)
Min Freq
Max Freq
TEMP (
o
C)
0
10
20
30
40
50
60
70
80
90
100
-60 -40 -20 0 20 40 60 80 100 120 140
0
2
4
6
8
10
12
14
-60 -40 -20 0 40 100 120 140
Gate Resistor (R
OH
, R
OL
) Temp (
o
C)
Z
out
(Ohm)
Source
Sink
V
DD
= 13 V
I
source
= 100 mA
I
sink
= 200 mA
20 60 80
-50 0 50 100 150
TEM P (
o
C)
Supply Current (mA)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Operating
V
DD
= 13 V
C
L
= 1 nF
f
SW(max)
= 70 kHz
Start-up
420
430
440
450
460
470
480
490
500
-50 0 50 100 150
Temperature (°C)
V
link
(V)
OVP
Normal
Figure 7. Supply Current (I
SB
, I
ST
, I
DD
) vs. Temp Figure 8. Min/Max Operating Frequency vs. Temp
Figure 9. Gate Resistance (R
OH
, R
OL
) vs. Temp Figure 10. OVP vs. Temp
CS1600
8 DS904F1
5. GENERAL DESCRIPTION
The CS1600 offers numerous features, options, and
functional capabilities to the designer of switching power
converters. This digital PFC control IC is designed to replace
legacy analog PFC controllers with minimal design effort.
5.1 PFC Operation
One key feature of the CS1600 is its operating frequency
profile. Figure 11 illustrates how the frequency varies over half
cycle of the line voltage in steady-state operation. When
power is first applied to the CS1600, it examines the line
voltage and adapts its operating frequency to the line voltage
as shown in Figure 11. The operating frequency is varied from
the peak to the trough of the AC input. During start-up the
control algorithm’s goal is to generate maximum power while
maintaining DCM operation, providing an approximate
square-wave envelop current within every half line cycle by
adjusting the operating frequency for fast startup behavior.
Figure 11. Switching Frequency vs. Phase Angle
Figure 12 illustrates how the operating frequency (as a
percentage of maximum frequency) changes with output
power and the peak of the line voltage.
Figure 12. Max Switching Frequency vs. Output Power
When P
o
falls below 5% the CS1600 changes to Burst Mode
(See 5.3 Burst Mode on page 8).
5.2 Start-up vs. Normal Operation Mode
CS1600 has two discrete operation modes: Start-up and
Normal. Start-up mode will be activated when V
link
is less than
90% of nominal value and remains active until V
link
reaches
100% of nominal value, as shown in Figure 13. Startup mode
is activated during initial system power-up. Any V
link
drop to
less than 90% of nominal value, such as load change, can
cause the system to enter Start-up mode until V
link
is brought
back into regulation.
Figure 13. Start-up and Normal Modes
Startup mode is defined as a surge of current delivering
maximum power to the output regardless of the load. During
every active switch cycle, the 'ON' time is calculated to drive a
constant peak current over the entire line cycle. However, the
'OFF' time is calculated based on the DCM/CCM boundary
equation.
5.3 Burst Mode
Burst mode is utilized to improve system efficiency when the
system output power (P
o
) is < 5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period cycle under light load conditions, as shown in
Figure 14.
Figure 14. Burst Modes
0
20
40
60
80
100
120
04590135180
Rectified Line Voltage Phase (Deg.)
% of Max
Switching Freq. (% of Max.)
Line Voltage (% of Max.)
% P
O max
F
SW max
(kHz)
20
70
50
60
40
405
Burst Mode
20
0
60 80 100
48
56
Vin > 156 VAC
Vin < 182 VAC
t [ms]
V
link
[V]
100%
90%
Startup Mode
Normal
Mode
Startup Mode
Normal
Mode
V
in
[V]
t [ms]
FET
V
gs
Burst Mode
Active
V
in
P
o
[W]
t [ms]
PFC
Disable
Burst Threshold
CS1600
DS904F1 9
5.4 Output Power and PFC Boost Inductor
In normal operating mode, the nominal output power is
estimated by the following equation.
where:
P
o
rated output power of the system
η efficiency of the boost converter (estimated as 100%
by the PFC algorithm)
V
in(min)
minimum RMS line voltage is 108V, measured after
the rectifier and EMI filter
V
link
nominal PFC output voltage must be 460 V
f
max
maximum switching frequency is 70 kHz
L
B
boost inductor specified by rated power requirement
α margin factor to guarantee rated output power (P
o
)
against boost inductor tolerances.
Equation 1 is provided for explanation purposes only. Using
substituted required design values for V
link
and f
max
gives the
following equation.
Changing values for application-specific devices such as the
boost inductor or V
link
voltage is not recommended and
requires changing internal register values.
Solving Equation 2 for the PFC boost inductor L
B
gives the
following equation.:
If a value of the boost inductor other than that obtained from
Equation 3 above is used, the total output power capability as
well as the minimum input voltage threshold will differ
according to Equation 2.
Figure 15. Relative Effects of Varying Boost Inductance
5.5 PFC Output Capacitor
The value of the PFC output capacitor should be chosen
based upon voltage ripple and hold-up requirements. To
ensure system stability with the digital controller, the
recommended value of the capacitor is within the range of
0.25 μF / watt to 0.5 μF/watt.
5.6 Output IFB Sense & Input IAC Sense
A current proportional to the PFC output voltage, V
link
, is
supplied to the IC on pin IFB and is used as a feedback control
signal. This current is compared against an internal fixed-
value current.
The ADC is used to measure the magnitude of the I
FB
current
through resistor R
IFB
. The magnitude of the I
FB
current is then
compared to an internal fixed-value current.
Figure 16. Feedback Input Pin Model
Resistor R
IFB
sets the feedback current and is calculated as
follows:
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
Figure 17. IAC Input Pin Model
Resistor R
IAC
sets the IAC current and is derived as follows:
For optimal performance, resistors R
IAC
&
R
IFB
should use 1%
tolerance or better resistors.
P
o
αη
V
in min()
()×
2
×
V
link
V
in min()
2×()–
2f
max
L
B
V
link
×××
---------------------------------------------------------
×=
[Eq.1]
P
o
αη 108V()×
2
×
460V 108V 2×()–
270kHz L
B
460V×××
-------------------------------------------------------------
×=
[Eq.2]
L
B
αη 108V()×
2
×
460V 108V 2×()–
270kHzP
o
460V×××
-------------------------------------------------------------
×=
[Eq.3]
V
AC(rms)
108 305
P
o(max)
L > L
B
/α
L = L
B
L < L
B
/α
IFB
VDD
15k
7
V
link
CS1600
24k
ADC
R3
R
IFB
I
FB
R4
4
R
IFB
V
link
V
dd
–
I
fixed
----------------------------
460V V
dd
–
129μA
------------------------------
==
[Eq.4]
R1
R
IAC
I
AC
IA C
VDD
15k
7
V
rect
CS1600
24k
ADC
R2
3
R
IAC
R
IFB
=
[Eq.5]
P1-P3P4-P6P7-P9P10-P12P13-P14

CS1600-FSZ

Mfr. #:
Buy CS1600-FSZ
Manufacturer:
Cirrus Logic
Description:
Power Factor Correction - PFC PFC CONTROLLER DCM MOD for Lighting
Lifecycle:
New from this manufacturer.
Delivery:
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