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low leakage. Capacitor leakage current must not exceed
the minimum TMR charging current of 1.3µA. Tying the
TMR pin to V
CC
bypasses the timeout period.
Undervoltage Lockout
When V
CC
falls below 2V, the LTC2914 asserts an under-
voltage lockout (UVLO)
condition. During UVLO, UV is
asserted and pulled low while OV is cleared and blocked
from asserting. When V
CC
rises above 2V, UV follows the
same timing procedure as an undervoltage condition on
any input.
Shunt Regulator
The LTC2914 has an internal shunt regulator. The V
CC
pin
operates as a direct supply input for voltages up to 6V.
Under this condition, the quiescent current of the device
remains below a maximum of 100µA. For V
CC
voltages
higher than 6V, the device operates as a shunt regulator
and must have a resistance R
Z
between the supply and
the V
CC
pin to limit the current to no greater than 10mA.
When choosing this resistance value, choose an appropriate
location on the I-V curve shown in the Typical Performance
Characteristics section to accommodate variations in V
CC
due to changes in current through R
Z
.
UV and OV Output Characteristics
The DC characteristics of the UV and OV pull-
up and
pull-down strength
are shown in the Typical Performance
Characteristics section. Each pin has a weak internal
pull-up to V
CC
and a strong pull-down to ground. This ar-
rangement allows these
pins to have open-drain behavior
while possessing several other beneficial characteristics.
The weak pull-up eliminates the need for an external pull-
up resistor when the rise time on the pin is not critical.
On the other hand, the open-drain configuration allows
for wired-OR connections and is useful when more than
one signal needs to pull down on the output. V
CC
of 1V
guarantees a maximum V
OL
= 0.15V at UV.
At V
CC
= 1V, the weak pull-up current on OV is barely turned
on. Therefore, an external pull-up resistor of no more
than 100k is recommended on the OV pin if the state and
pull-up strength of the OV pin is crucial at very low V
CC
.
Note however, by adding an external pull-up resistor, the
pull-up strength on the OV pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device must accommodate this
additional pull
-up strength.
Output Rise and Fall Time Estimation
The UV
and OV outputs have strong pull-down capability.
The following formula estimates the output fall time (90%
to 10%) for a particular external load capacitance (C
LOAD
):
t
FALL
≈ 2.2 • R
PD
• C
LOAD
where R
PD
is the on-resistance of the internal pull-down
transistor, typically 50Ω at V
CC
> 1V and at room tem-
perature (25°C). C
LOAD
is the external load capacitance
on the pin. Assuming a 150pF load capacitance, the fall
time is 16.5ns.
The rise time on the UV and OV pins is limited by a 400k
pull-up resistance to V
CC
. A similar formula estimates the
output rise time (10% to 90%) at the UV and OV pins:
t
RISE
≈ 2.2 • R
PU
• C
LOAD
where R
PU
is the pull-up resistance.
OV Latch (LTC2914-1)
With the LATCH pin held low, the OV pin latches low
when an OV condition is detected. The latch is cleared by
raising the LATCH pin high. If an OV condition changes
while LATCH is held high, the latch is bypassed and the
OV pin behaves the same as the UV pin with a similar
timeout period at the output. If LATCH is pulled low while
the
timeout period is
active, the OV pin latches as before.
Disable (LTC2914-2)
The LTC2914-2 allows disabling the UV and OV outputs via
the DIS pin. Pulling DIS high forces both outputs to remain
weakly pulled high, regardless of any faults that occur on
the inputs. However, if a UVLO condition occurs, UV as
-
serts and pulls low, but the timeout function is bypassed.
UV pulls high as soon as the UVLO condition is cleared.
DIS has a weak 2µA (typical) internal pull-down current
guaranteeing normal operation with the pin left open.
applicaTions inForMaTion
