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5V49EE503NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 10
IDT5V49EE503 REV Q 071015
Spread Spectrum Generation (PLL3)
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
and SSVCO (spread spectrum loop feedback counter).
SS is the total Spread Spectrum amount (I.e. center spread
+
0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
Loop Filter
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0
kOhm
Zero capacitor (Cz) = 196 pF + CZ* 217 pF
Pole capacitor (Cp) = 15 pF
Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA
VCO gain (K
VCO) = 900 MHz/V * 2
The following equations govern how the loop filter is set for
PLL3:
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
Zero capacitor (Cz) = 250 pF
Pole capacitor (Cp) = 15 pF
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
VCO gain (K
VCO) = 900 MHz/V * 2
=
SS_D3
(Eq. 10)
F
IN
4 * F
MOD
SSVCO
=
F
VCO
F
MOD
[0.5 *
*
(Eq. 11)
( 1 + SS/400) + 5]
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 11
IDT5V49EE503 REV Q 071015
PLL Loop Bandwidth:
Charge pump gain (K) = Ip / 2
VCO gain (K
VCO) = 900 MHz/V * 2
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
c = (Rz * K* K
VCO * Cz)/(M * (Cz + Cp))
Fc = c / 2
Note, the phase/frequency detector frequency (F
PFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (m)
needs to be calculated as follows.
Phase Margin:
z = 1 / (Rz * Cz)
p = (Cz + Cp)/(Rz * Cz * Cp)
m = (360 / 2) * [tan
-1(c/ z) - tan-1(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 12
IDT5V49EE503 REV Q 071015
SEL[2:0] Function
The IDT5V49EE503 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
pins. Alternatively, users may use I
2
C interface to configure
these registers on-the-fly.
Crystal/Clock Selection
XTCLKSEL bit is used to bypass a crystal oscillator circuit
when external clock source is used.
PRIMSRC bit is used to select a primary clock from
XIN/REF and CLKIN.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active LOW and when
SP is “1”, the pin becomes active HIGH. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
SEL2 SEL1 SEL0 Configuration Selections
00 0Select CONFIG0
00 1Select CONFIG1
01 0Select CONFIG2
01 1Select CONFIG3
10 0Select CONFIG4
10 1Select CONFIG5
1 1 0 Reserved (Do not use)
1 1 1 Reserved (Do not use)
PRIMSRC bit Primary Secondary
0XIN/REFCLKIN
1 CLKIN XIN/REF
CLKSEL input
0
1
CLKSEL PRIMSRC Reference Clock
0 0 XIN/REF
01CLKIN
10CLKIN
1 1 XIN/REF
Clock Source
Primary Clock Source
Secondary Clock Source
SMx[1:0] Swithcing Mode
Primary to
Secondary
Secondary to
Primary
0x Manual No No
10 Auto Yes No
11 Auto-Revertive Yes Yes
OUTn
OS
OE
SP
SD/OE Input
SH
Global Shutdown
Truth Table
SH bit SP bit OSn bit OEn bit SD/OE OUTn
0 0 0 x x High-Z
2
0 0 1 0 x Enabled
0 0 1 1 0 Enabled
0 0 1 1 1 Suspended
0 1 0 x x High-Z
2
0 1 1 0 x Enabled
0 1 1 1 0 Suspended
0 1 1 1 1 Enabled
1 0 0 x 0 High-Z
2
1 0 1 0 0 Enabled
1 0 1 1 0 Enabled
1 1 0 x 0 High-Z
2
1 1 1 0 0 Enabled
1 1 1 1 0 Suspended
1x x x 1
Suspended
1
Note 1 : Global Shutdown
Note 2 : Hi-Z regardless of OEM bits
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

5V49EE503NLGI

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Manufacturer:
IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
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