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5V49EE503NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 22
IDT5V49EE503 REV Q 071015
0x28 00
Reserved D1[6:0]_CFG0
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
0x29 00
Reserved D1[6:0]_CFG1
0x2A 00
Reserved D1[6:0]_CFG2
0x2B 00
Reserved D1[6:0]_CFG3
0x2C 00
Reserved D1[6:0]_CFG4
0x2D 00
Reserved D1[6:0]_CFG5
0x2E 01
N1[7:0]_CFG4
N - Feedback Divider
2 - 4095 (value of “0” is not
allowed) Total feedback with A,
using provided calculation
0x2F 01
N1[7:0]_CFG5
0x30 01
N1[7:0]_CFG0
0x31 01
N1[7:0]_CFG1
0x32 01
N1[7:0]_CFG2
0x33 01
N1[7:0]_CFG3
0x34 00
N3[11:8]_CFG0 N1[11:8]_CFG0
PLL3 Feedback Divider
0x35 00
N3[11:8]_CFG1 N1[11:8]_CFG1
0x36 00
N3[11:8]_CFG2 N1[11:8]_CFG2
0x37 00
N3[11:8]_CFG3 N1[11:8]_CFG3
0x38 00
N3[11:8]_CFG4 N1[11:8]_CFG4
0x39 00
N3[11:8]_CFG5 N1[11:8]_CFG5
0x3A 00
CZ2_CFG4 IP2[2:0]_CFG4 RZ2[3:0]_CFG4
PLL2 Loop Parameter
0x3B 00
CZ2_CFG5 IP2[2:0]_CFG5 RZ2[3:0]_CFG5
0x3C 00
CZ2_CFG0 IP2[2:0]_CFG0 RZ2[3:0]_CFG0
0x3D 00
CZ2_CFG1 IP2[2:0]_CFG1 RZ2[3:0]_CFG1
0x3E 00
CZ2_CFG2 IP2[2:0]_CFG2 RZ2[3:0]_CFG2
0x3F 00
CZ2_CFG3 IP2[2:0]_CFG3 RZ2[3:0]_CFG3
0x40 00
Reserved D2[6:0]_CFG0
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
0x41 00
Reserved D2[6:0]_CFG1
0x42 00
Reserved D2[6:0]_CFG2
0x43 00
Reserved D2[6:0]_CFG3
0x44 00
Reserved D2[6:0]_CFG4
0x45 00
Reserved D2[6:0]_CFG5
0x46 01
N2[7:0]_CFG4
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for
N2[15:8])
0x47 01
N2[7:0]_CFG5
0x48 01
N2[7:0]_CFG0
0x49 01
N2[7:0]_CFG1
0x4A 01
N2[7:0]_CFG2
0x4B 01
N2[7:0]_CFG3
0x4C 80
SSENB_CFG0 0 0
IP3[4]_CFG0
N2[11:8]_CFG0
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum
Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
0x4D 80
SSENB_CFG1 0 0
IP3[4]_CFG1
N2[11:8]_CFG1
0x4E 80
SSENB_CFG2 0 0
IP3[4]_CFG2
N2[11:8]_CFG2
0x4F 80
SSENB_CFG3 0 0
IP3[4]_CFG3
N2[11:8]_CFG3
0x50 80
SSENB_CFG4 0 0
IP3[4]_CFG4
N2[11:8]_CFG4
0x51 80
SSENB_CFG5 0 0
IP3[4]_CFG5
N2[11:8]_CFG5
0x52 XX
1
Reserved
0x53 XX
1
Reserved
0x54 XX
1
Reserved
0x55 XX
1
Reserved
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 23
IDT5V49EE503 REV Q 071015
0x56 00
IP3[3:0]_CFG4 RZ3[3:0]_CFG4
PLL3 Loop Parameter
0x57 00
IP3[3:0]_CFG5 RZ3[3:0]_CFG5
0x58 00
IP3[3:0]_CFG0 RZ3[3:0]_CFG0
0x59 00
IP3[3:0]_CFG1 RZ3[3:0]_CFG1
0x5A 00
IP3[3:0]_CFG2 RZ3[3:0]_CFG2
0x5B 00
IP3[3:0]_CFG3 RZ3[3:0]_CFG3
0x5C 03
Reserved D3[6:0]_CFG0
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
0x5D 03
Reserved D3[6:0]_CFG1
0x5E 03
Reserved D3[6:0]_CFG2
0x5F 03
Reserved D3[6:0]_CFG3
0x60 03
Reserved D3[6:0]_CFG4
0x61 03
Reserved D3[6:0]_CFG5
0x62 0C
N3[7:0]_CFG4
N - Feedback Divider
12 - 4095 (values of “0” through
“11” are not allowed)
0x63 0C
N3[7:0]_CFG5
0x64 0C
N3[7:0]_CFG0
0x65 0C
N3[7:0]_CFG1
0x66 0C
N3[7:0]_CFG2
0x67 0C
N3[7:0]_CFG3
0x68 00
SSVCO[7:0]_CFG0
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback
Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
0x69 00
SSVCO[7:0]_CFG1
0x6A 00
SSVCO[7:0]_CFG2
0x6B 00
SSVCO[7:0]_CFG3
0x6C 00
SSVCO[7:0]_CFG4
0x6D 00
SSVCO[7:0]_CFG5
0x6E 00
SS_D3[7:0]_CFG4
SS_D[7:0] - PLL3 Spread
Spectrum Reference Divide
0x6F 00
SS_D3[7:0]_CFG5
0x70 00
SS_D3[7:0]_CFG0
0x71 00
SS_D3[7:0]_CFG1
0x72 00
SS_D3[7:0]_CFG2
0x73 00
SS_D3[7:0]_CFG3
0x74 01
Reserved
Reserved
0x75 03
OEM0[1:0] SLEW0[1:0] INV0 Reserved S1 S3
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
0x76 00
OEM1[1:0] SLEW1[1:0] INV1[1:0] Reserved
Output Controls
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OUT1/OUT2
0x77 00
SLEW2[1:0] Reserved
0x78 00
OEM3[1:0] SLEW3[1:0] INV3[1:0] Reserved
OEM3 controls OUT3 and OUT6
0x79 00
Reserved
0x7A 00
Reserved
0x7B 00
SLEW6[1:0] Reserved
0x7C XX
1
Reserved
0x7D XX
1
Reserved
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
IDT5V49EE503
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 24
IDT5V49EE503 REV Q 071015
0x7E XX
1
Reserved
0x7F XX
1
Reserved
0x80 00
SSVCO[15:8]_CFG0
PLL3 Spread Spectrum Feedback
Counter
0x81 00
SSVCO[15:8]_CFG1
0x82 00
SSVCO[15:8]_CFG2
0x83 00
SSVCO[15:8]_CFG3
0x84 00
SSVCO[15:8]_CFG4
0x85 00
SSVCO[15:8]_CFG5
0x86 00
Reserved
0x87 00
Reserved
0x88 FF
PM1_CFG0 Q1[6:0]_CFG0
Output Divides
for Q<>111111,
PM=0 - Divide by 2
PM=1, (Q+2)*2
for Q=1111111
PM=0, disable the output divider
PM=1, bypass the output divide,
(divide by 1)
0x89 FF
PM1_CFG1 Q1[6:0]_CFG1
0x8A FF
PM1_CFG2 Q1[6:0]_CFG2
0x8B FF
PM1_CFG3 Q1[6:0]_CFG3
0x8C FF
PM1_CFG4 Q1[6:0]_CFG4
0x8D FF
PM1_CFG5 Q1[6:0]_CFG5
0x8E 7F
PM2_CFG4 Q2[6:0]_CFG4
0x8F 7F
PM2_CFG5 Q2[6:0]_CFG5
0x90 7F
PM2_CFG0 Q2[6:0]_CFG0
0x91 7F
PM2_CFG1 Q2[6:0]_CFG1
0x92 7F
PM2_CFG2 Q2[6:0]_CFG2
0x93 7F
PM2_CFG3 Q2[6:0]_CFG3
0x94 7F
PM3_CFG0 Q3[6:0]_CFG0
0x95 7F
PM3_CFG1 Q3[6:0]_CFG1
0x96 7F
PM3_CFG2 Q3[6:0]_CFG2
0x97 7F
PM3_CFG3 Q3[6:0]_CFG3
0x98 7F
PM3_CFG4 Q3[6:0]_CFG4
0x99 7F
PM3_CFG5 Q3[6:0]_CFG5
0x9A 7F
Reserved
0x9B 7F
Reserved
0x9C 7F
Reserved
0x9D 7F
Reserved
0x9E 7F
Reserved
0x9F 7F
Reserved
0xA0 7F
Reserved
0xA1 7F
Reserved
0xA2 7F
Reserved
0xA3 7F
Reserved
0xA4 7F
Reserved
0xA5 7F
Reserved
0xA6 7F
PM6_CFG4 Q6[6:0]_CFG4
0xA7 7F
PM6_CFG5 Q6[6:0]_CFG5
0xA8 7F
PM6_CFG0 Q6[6:0]_CFG0
0xA9 7F
PM6_CFG1 Q6[6:0]_CFG1
0xAA 7F
PM6_CFG2 Q6[6:0]_CFG2
0xAB 7F
PM6_CFG3 Q6[6:0]_CFG3
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

5V49EE503NLGI

Mfr. #:
Buy 5V49EE503NLGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
Lifecycle:
New from this manufacturer.
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