7
LTC1292/LTC1297
12927fb
Load Circuit for t
dis
and t
en
Load Circuit for t
dDO
, t
r
and t
f
On and Off Channel Leakage Current
Voltage Waveforms for D
OUT
Delay Time, t
dDO
W
IDAGRA
B
L
O
C
K
TEST CIRCUITS
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Voltage Waveforms for t
dis
INPUT
SHIFT
REGISTER
COMP
SAMPLE
AND
HOLD
12-BIT
CAPACITIVE
DAC
OUTPUT
SHIFT
REGISTER
12-BIT
SAR
CONTROL
AND
TIMING
V
CC
8
ANALOG
INPUT MUX
2
3
V
REF
5
GND
4
–IN
+IN
D
OUT
6
1
CLK
7
CS
LTC1292/7 BD
D
OUT
1.4V
3k
100pF
TEST POINT
LTC1292/7 TC03
D
OUT
3k
100pF
TEST POINT
5V t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
LTC1292/7 TC02
5V
A
A
I
OFF
I
ON
POLARITY
OFF CHANNEL
ON CHANNEL
LTC1292/7 TC01
CLK
D
OUT
0.8V
t
dDO
0.4V
2.4V
LTC1292/7 TC04
D
OUT
0.4V
2.4V
t
r
t
f
LTC1292/7 TC05
D
OUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
t
dis
90%
10%
D
OUT
WAVEFORM 2
(SEE NOTE 2)
CS
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1292/7 TC06
8
LTC1292/LTC1297
12927fb
TEST CIRCUITS
Voltage Waveforms for t
en
The LTC1292/LTC1297 are data acquisition components
which contain the following functional blocks:
1. 12-Bit Succesive Approximation Capacitive A/D
Converter
2. Differential Input
3. Sample-and-Hold (S/H)
4. Synchronous, Half-Duplex Serial Interface
5. Control and Timing Logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1292/LTC1297 communicate with microproces-
sors and other external circuitry via a synchronous, half-
duplex, three-wire serial interface (see Operating Se-
quence). The clock (CLK) synchronizes the data transfer
with each bit being transmitted on the falling CLK edge.
The LTC1292/LTC1297 do not require a configuration
input word and have no D
IN
pin. They are permanently
configured to have a single differential input and to per-
form a unipolar conversion. A falling CS initiates data
transfer. To allow the LTC1297 to recover from the power
shutdown mode, t
suCS
has to be met. Then the first CLK
pulse enables D
OUT
. After one null bit, the A/D conversion
result is output on the D
OUT
line with a MSB-first sequence
followed by a LSB-first sequence. With the half-duplex
serial interface the D
OUT
data is from the current conver-
sion. This provides easy interface to MSB-first or LSB-first
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
serial ports. Bringing CS high resets the LTC1292/LTC1297
for the next data exchange and puts the LTC1297 into its
power shutdown mode.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1292/LTC1297**
D
OUT
0.8V
t
en
B11
CS
CLK
LTC1292/7 TC07
PART NUMBER TYPE OF INTERFACE
Motorola
MC6805S2, S3 SPI
MC68HC11 SPI
MC68HC05 SPI
RCA
CDP68HC05 SPI
Hitachi
HD6305 SCI Synchronous
HD6301 SCI Synchronous
HD63701 SCI Synchronous
HD6303 SCI Synchronous
HD64180 SCI Synchronous
National Semiconductor
COP400 Family MICROWIRE
COP800 Family MCROWIRE/PLUS
NS8050U MICROWIRE/PLUS
HPC16000 Family MICROWIRE/PLUS
Texas Instruments
TMS7002 Serial Port
TMS7042 Serial Port
TMS70C02 Serial Port
TMS70C42 Serial Port
TMS32011* Serial Port
TMS32020* Serial Port
TMS370C050 SPI
* Requires external hardware
** Contact factory for interface information for processors not on this list
MICROWIRE and MICROWIRE/PLUS are trademarks of National
Semiconductor Corp.
9
LTC1292/LTC1297
12927fb
LTC1292 Operating Sequence
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB
first and in 8-bit increments. A dummy D
IN
word sent to the
data register starts the SPI process. With two 8-bit transfers,
the A/D result is read into the MPU (Figure 1). For the
LTC1292 the first 8-bit transfer clocks B11 through B8 of
the A/D conversion result into the processor. The second
8-bit transfer clocks the remaining bits B7 through B0 into
Microprocessor Interfaces
The LTC1292/LTC1297 can interface directly (without
external hardware) to most popular microprocessors’
(MPU) synchronous serial formats (see Table 1). If an
MPU without a dedicated serial port is used, then three of
the MPU’s parallel port lines can be programmed to form
the serial link to the LTC1292/LTC1297. Included here are
one serial interface example and one example showing a
parallel port programmed to form the serial interface.
Figure 1. Data Exchange Between LTC1292 and MC68HC11
CLK
t
CYC
CS
B11
B10B9B8
B7
B6
B5B4
B3
B2
B1
B0B1B2
B3
B4
B5B6
B7
B8
B9B10
B11
t
CONV
D
OUT
Hi-Z
t
SMPL
t
SMPL
LTC1292/7 AI01
LTC1297 Operating Sequence
CLK
CS
D
OUT
MPU
RECEIVED WORD
LTC1292/7 F01
B7
B6
B5 B4
B3 B2
B1
B0
B1
B8
B9
B10
B11
BYTE 2
B10 B9
B8B11
O
?
?
?
1ST TRANSFER
2ND TRANSFER
BYTE 1
B2 B1
B0
B3B4
B6
B7
B5
CLK
t
CYC
CS
B11
B10B9B8
B7
B6
B5B4
B3
B2
B1
B0B1B2
B3
B4
B5B6
B7
B8
B9B10
B11
t
CONV
D
OUT
Hi-Z
t
SMPL
LTC1292/7 AI02
t
suCS
POWER SHUTDOWN MODE

LTC1292CIN8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit Serial I/O Diff Input ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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