MAX1034/MAX1035
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be inde-
pendently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±6V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered.
Any voltage beyond FSR, but within the ±6V fault-
tolerant range, applied to an analog input results in a
full-scale output voltage for that channel.
Clamping diodes with breakdown thresholds in excess
of 6V protect the MAX1034/MAX1035 analog inputs
during ESD and other transient events (Figure 6). The
clamping diodes do not conduct during normal device
operation, nor do they limit the current during such
transients. When operating in an environment with the
potential for high-energy voltage and/or current tran-
sients, protect the MAX1034/MAX1035 externally.
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 14-Bit ADCs
16 ______________________________________________________________________________________
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIN SC2C1C00000
ANALOG INPUT
TRACK AND HOLD*
HOLD
DOUT
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X
BYTE 1 BYTE 2 BYTE 3 BYTE 4
SSTRB
INTCLK**
1
2
3
14
15
16
17
TRACK HOLD
t
ACQ
100ns to 400ns
f
INTCLK
4.5MHz
f
SAMPLE
f
SCLK
/ 32 + f
INTCLK
/ 17
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
HIGH
IMPEDANCE
Figure 3. External Acquisition-Mode Conversion (Mode 1)
Figure 6. Simplified Analog Input Circuit
MAX1034
MAX1035
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
IN_+
IN_+
*MINIMIZE R
SOURCE
TO AVOID GAIN ERROR AND DISTORTION.
MAX1034/MAX1035
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 14-Bit ADCs
______________________________________________________________________________________ 17
CS
SCLK
1
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
DIN S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
TRACK
DOUT
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X
BYTE 1 BYTE 2 BYTE 3
SSTRB
INTCLK**
1
2
3
25
26
27
28
9
10
11
12
13
14
15
16
10
11
12
13
14
HOLD HOLD
t
ACQ
100ns to 400ns
f
INTCLK
4.5MHz
f
SAMPLE
f
SCLK
/ 24 + f
INTCLK
/ 28
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
HIGH IMPEDANCE
Figure 4. Internal Clock-Mode Conversion (Mode 2)
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT CURRENT (mA)
420-2-4
-0.5
-1.0
0
0.5
1.0
1.5
-1.5
-6 6
Figure 5. Analog Input Current vs. Input Voltage
MAX1034/MAX1035
Differential Common-Mode Range
The MAX1034/MAX1035 differential common-mode
range (V
CMDR
) must remain within -4.75V to +5.5V to
obtain valid conversion results. The differential com-
mon-mode range is defined as:
In addition to the common-mode input voltage limita-
tions, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input configu-
ration bytes determine the full-scale range for the corre-
sponding channel (Tables 2 and 6). Figures 9, 10, and
11 show the valid analog input voltage ranges for
the MAX1034/MAX1035 when operating with FSR =
V
REF
/ 2, FSR = V
REF
, and FSR = 2 x V
REF
, respectively.
The shaded area contains the valid common-mode
voltage ranges that support the entire FSR.
V
CH CH
CMDR
_ _
=
+
()
+
()
2
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 14-Bit ADCs
18 ______________________________________________________________________________________
Table 3. Input Data Word Formats
DATA BIT
OPERATION
D7
(START)
D6 D5 D4 D3 D2 D1 D0
Conversion-Start Byte
(Tables 4 and 5)
1C2C1C00000
Analog-Input Configuration Byte
(Table 2)
1 C2 C1 C0 DIF/SGL R2 R1 R0
Mode-Control Byte
(Table 7)
1M2M1M01000
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
CHANNEL-SELECT BIT CHANNEL
C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1
000+ -
001 + -
010 + -
011 + -
100 + -
101 + -
110 +-
111 +-
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
CHANNEL-SELECT BIT CHANNEL
C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1
000+-
0 0 1 RESERVED
010 +-
0 1 1 RESERVED
100 +-
1 0 1 RESERVED
110 +-
1 1 1 RESERVED

MAX1034BEUG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 8-/4-Channel Multirange Inputs
Lifecycle:
New from this manufacturer.
Delivery:
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