MAX1034BEUG+ Datasheet MAX1035EUP+, MAX1034BEUG+, MAX1034BEUG+T | P19-P21

Digital Interface

The MAX1034/MAX1035 feature a serial interface that is

compatible with SPI/QSPI and MICROWIRE devices.

DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirection-

al communication between the MAX1034/MAX1035 and

the master at SCLK rates up to 10MHz (internal clock

mode, mode 2), 3.67MHz (external clock mode, mode

0), or 4.39MHz (external acquisition mode, mode 1).

The master, typically a microcontroller, should use the

CPOL = 0, CPHA = 0, SPI transfer format, as shown in

the timing diagrams of Figures 2, 3, and 4.

The digital interface is used to:

• Select single-ended or true-differential input channel

configurations

• Select the unipolar or bipolar input range

• Select the mode of operation:

External clock (mode 0)

External acquisition (mode 1)

Internal clock (mode 2)

Reset (mode 4)

Partial power-down (mode 6)

Full power-down (mode 7)

• Initiate conversions and read results

Chip Select (CS)

CS enables communication with the MAX1034/MAX1035.

When CS is low, data is clocked into the device from DIN

on the rising edge of SCLK and data is clocked out of

DOUT on the falling edge of SCLK. When CS is high,

activity on SCLK and DIN is ignored and DOUT is high

impedance allowing DOUT to be shared with other

peripherals. SSTRB is never high impedance and there-

fore cannot be shared with other peripherals.

Serial-Strobe Output (SSTRB)

As shown in Figures 3 and 4, the SSTRB transitions high

to indicate that the ADC has completed a conversion

and results are ready to be read by the master. SSTRB

remains low in the external clock mode (Figure 2) and

consequently may be left unconnected. SSTRB is driven

high or low regardless of the state of CS, therefore

SSTRB cannot be shared with other peripherals.

MAX1034/MAX1035

8-/4-Channel, ±V

REF

Multirange Inputs,

Serial 14-Bit ADCs

______________________________________________________________________________________ 19

001

010

011

100

101

110

111

-V

REF

-3/4 V

REF

-V

REF

+3/4 V

REF

-V

REF

EACH INPUT IS FAULT TOLERANT TO ±6V.

(CH_) - AGND1 (V)

INPUT RANGE SELECTION BITS, R[2:0]

FSR = V

REF

/ 2

FSR = V

REF

/ 2

FSR = V

REF

/ 2

FSR = V

REF

FSR = V

REF

FSR = V

REF

FSR = 2 x V

REF

Figure 7. Single-Ended Input Voltage Ranges

001

010

011

100

101

110

111

-V

REF

-3/2 V

REF

-2 x V

REF

+3/2 V

REF

-V

REF

EACH INPUT IS FAULT TOLERANT TO ±6V.

(CH_+) - (CH_-) (V)

INPUT RANGE SELECTION BITS, R[2:0]

FSR = V

REF

FSR = 2 x V

REF

FSR = 4 x V

REF

Figure 8. Differential Input Voltage Ranges

MAX1034/MAX1035

8-/4-Channel, ±V

REF

Multirange Inputs,

Serial 14-Bit ADCs

20 ______________________________________________________________________________________

Table 6. Range-Select Bits

DIF/SGL R2 R1 R0 MODE TRANSFER FUNCTION

0 0 0 0 No Range Change* —

0001

Single-Ended

Bipolar - V

REF

/4 to +V

REF

Full-Scale Range (FSR) = V

REF

/ 2

Figure 12

0010

Single-Ended

Unipolar -V

REF

/2 to 0

FSR = V

REF

/ 2

Figure 13

0011

Single-Ended

Unipolar 0 to +V

REF

FSR = V

REF

/ 2

Figure 14

0100

Single-Ended

Bipolar -V

REF

/2 to +V

REF

FSR = V

REF

Figure 12

0101

Single-Ended

Unipolar -V

REF

to 0

FSR = V

REF

Figure 13

0110

Single-Ended

Unipolar 0 to +V

REF

FSR = V

REF

Figure 14

0111

DEFAULT SETTING

Single-Ended

Bipolar -V

REF

to +V

REF

FSR = 2 x V

REF

Figure 12

1 0 0 0 No Range Change** —

1001

Differential

Bipolar -V

REF

/2 to +V

REF

FSR = V

REF

Figure 12

1 0 1 0 Reserved —

1 0 1 1 Reserved —

1100

Differential

Bipolar -V

REF

to +V

REF

FSR = 2 x V

REF

Figure 12

1 1 0 1 Reserved —

1 1 1 0 Reserved —

1111

Differential

Bipolar -2 x V

REF

to +2 x V

REF

FSR = 4 x V

REF

Figure 12

Conversion-Start Byte (see Table 3).

Mode-Control Byte (see Table 3).

MAX1034/MAX1035

8-/4-Channel, ±V

REF

Multirange Inputs,

Serial 14-Bit ADCs

______________________________________________________________________________________ 21

Start Bit

Communication with the MAX1034/MAX1035 is accom-

plished using the three input data word formats shown

in Table 3. Each input data word begins with a start bit.

The start bit is defined as the first high bit clocked into

DIN with CS low when any of the following are true:

• Data conversion is not in process and all data from

the previous conversion has clocked out of DOUT.

• The device is configured for operation in external

clock mode (mode 0) and previous conversion-result

bits B13–B1 have clocked out of DOUT.

• The device is configured for operation in external

acquisition mode (mode 1) and previous conversion-

result bits B13–B5 have clocked out of DOUT.

• The device is configured for operation in internal

clock mode (mode 2) and previous conversion-

result bits B13–B2 have clocked out of DOUT.

Output Data Format

Output data is clocked out of DOUT in offset binary for-

mat on the falling edge of SCLK, MSB first (B13). For

output binary codes, see the

Transfer Function

section

and Figures 12, 13, and 14.

Configuring Analog Inputs

Each analog input has two configurable parameters:

• Single-ended or true-differential input

• Input voltage range

These parameters are configured using the analog input

configuration byte as shown in Table 2. Each analog

input has a dedicated register to store its input configura-

tion information. The timing diagram of Figure 15 shows

how to write to the analog input configuration registers.

Figure 16 shows DOUT and SSTRB timing.

Transfer Function

An ADC’s transfer function defines the relationship

between the analog input voltage and the digital output

code. Figures 12, 13, and 14 show the MAX1034/

MAX1035 transfer functions. The transfer function is

determined by the following characteristics:

• Analog input voltage range

• Single-ended or differential configuration

• Reference voltage

The axes of an ADC transfer function are typically in least

significant bits (LSBs). For the MAX1034/MAX1035, an

LSB is calculated using the following equation:

where N is the number of bits (N = 14) and FSR is the

full-scale range (see Figures 7 and 8).

2 4 096

LSB

FSR V

REF

INPUT COMMON-MODE VOLTAGE RANGE

vs. OUTPUT VOLTAGE (FSR = V

REF

)

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

6420-2-4-6

-4

-2

-6

-8 8

REF

= 4.096V

Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = V

REF

)

INPUT COMMON-MODE VOLTAGE RANGE

vs. OUTPUT VOLTAGE (FSR = 2 x V

REF

)

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

6420-2-4-6

-4

-2

-6

-8 8

REF

= 4.096V

Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x

REF

)

INPUT COMMON-MODE VOLTAGE RANGE

vs. OUTPUT VOLTAGE (FSR = 4 x V

REF

)

INPUT VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

6420-2-4-6

-4

-2

-6

-8 8

REF

= 4.096V

Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x

REF

)

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MAX1034BEUG+

Mfr. #:

Buy MAX1034BEUG+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 8-/4-Channel Multirange Inputs

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MAX1034BEUG+

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