Quad, 14-Bit, 125 MSPS Serial LVDS 1.8 V
Analog-to-Digital Converter
Preliminary Technical Data
AD9253-EP
Rev. PrA
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FEATURES
1.8 V supply operation
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Qualification data available on request
Low power: 110 mW per channel at 125 MSPS
SNR = 74 dB (to Nyquist)
SFDR = 90 dBc (to Nyquist)
DNL = ±0.8 LSB (typical); INL = ±2.0 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced signal
option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The AD9253-EP is a quad, 14-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip, sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and
low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are required
for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
designed to maximize flexibility and minimize system cost, such as
programmable output clock and data alignment and digital test
pattern generation. The available digital test patterns include
built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the serial port
interface (SPI).
The AD9253-EP is available in a RoHS-compliant, 48-lead LFCSP
and is specified over an extended temperature range of −55°C to
+125°C. This product is protected by a U.S. patent. Additional
application and technical information can be found in the AD9253
data sheet.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 110 mW/channel at 125 MSPS with scalable
power options.
3. Ease of Use. A DCO operates at frequencies of up to 500 MHz
and supports double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
AD9253-EP
10065-001
VDD PDWN DRVDD
REF
SELECT
VIN–A
VIN+A
VIN–B
VIN+B
VIN–D
VIN+D
VIN–C
VIN+C
SENSE
AGND
SYNC
VCM
VREF
D0–A
D0+A
D0–B
D0+B
D1–B
D1+B
D1–C
D1+C
D0–C
D0+C
D1–D
D1+D
DCO–
DCO+
D0–D
D0+D
FCO–
FCO+
D1–A
D1+A
CLK+
CLK–
CSB
SDIO/OLM
SCLK/DTP
RBIAS
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
SERIAL
LVDS
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
CLOCK
MANAGEMENT
SERIAL PORT
INTERFACE
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
PIPELINE
ADC
14
14
14
14
1V
