AD9253TCPZR7-125EP Datasheet AD9253TCPZ-125EP, AD9253TCPZR7-125EP | P7-P9

Preliminary Technical Data AD9253-EP

Rev. PrA | Page 7 of 12

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Electrical

AVDD to AGND −0.3 V to +2.0 V

DRVDD to AGND −0.3 V to +2.0 V

Digital Outputs (D0±x, D1±x, DCO+,

DCO−, FCO+, FCO−) to AGND

−0.3 V to +2.0 V

CLK+, CLK− to AGND −0.3 V to +2.0 V

VIN+x, VIN−x to AGND −0.3 V to +2.0 V

SCLK/DTP, SDIO/OLM, CSB to AGND −0.3 V to +2.0 V

SYNC, PDWN to AGND −0.3 V to +2.0 V

RBIAS to AGND −0.3 V to +2.0 V

VREF, SENSE to AGND −0.3 V to +2.0 V

Environmental

Operating Temperature Range (Ambient) −55°C to +125°C

Maximum Junction Temperature 150°C

Lead Temperature (Soldering, 10 sec) 300°C

Storage Temperature Range (Ambient) −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

Table 6.

Package

Type

Air Flow

Velocity

(m/sec)

θ

JA

1

Ψ

JT

Ψ

JB

θ

JC

TOP

θ

JC

BOTTOM

Unit

48-Lead

LFCSP

0.0 20.3 0.10 5.9 6.1 1.0 °C/W

1.0 17.6 0.16 N/A

2

N/A

2

N/A

2

°C/W

2.5 16.5 0.20 N/A

2

N/A

2

N/A

2

°C/W

1

θ

JA

for a 4-layer printed circuit board (PCB) with solid ground plane (simulated).

Exposed pad soldered to PCB.

2

N/A = not applicable.

ESD CAUTION

AD9253-EP Preliminary Technical Data

Rev. PrA | Page 8 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

0

AGND,

Exposed Pad

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the

analog ground for the part. This exposed pad must be connected to ground for proper operation.

1

VIN+D ADC D Analog Input True.

2

VIN−D ADC D Analog Input Complement.

3, 4, 7, 34, 39, 45, 46

AVDD 1.8 V Analog Supply Pins.

5, 6

CLK−, CLK+ Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

8, 29

DRVDD Digital Output Driver Supply.

9

D1−D Channel D Digital Output 1 Complement.

10 D1+D Channel D Digital Output 1 True.

11 D0−D Channel D Digital Output 0 Complement.

12 D0+D Channel D Digital Output 0 True.

13

D1−C Channel C Digital Output 1 Complement.

14 D1+C Channel C Digital Output 1 True.

15

D0−C Channel C Digital Output 0 Complement.

16 D0+C Channel C Digital Output 0 True.

17

DCO− Data Clock Output Complement.

18 DCO+ Data Clock Output True.

19

FCO− Frame Clock Output Complement.

20 FCO+ Frame Clock Output True.

21

D1−B Channel B Digital Output 1 Complement.

22 D1+B Channel B Digital Output 1 True.

23

D0−B Channel B Digital Output 0 Complement.

24 D0+B Channel B Digital Output 0 True.

25 D1−A Channel A Digital Output 1 Complement.

26 D1+A Channel A Digital Output 1 True.

27 D0−A Channel A Digital Output 0 Complement.

28 D0+A Channel A Digital Output 0 True.

1

2

3

VIN+A

VIN–A

AVDD

4

PDWN

5

CSB

6

SDIO/OLM

7

SCLK/DTP

2

4

D

0

+

B

2

3

D

0

–

B

2

D

1

+

B

2

1

D

1

–

B

2

0

F

C

O

+

1

9

F

C

O

–

1

8

D

C

O

+

1

7

D

C

O

–

1

6

D

0

+

C

1

5

D

0

–

C

1

4

D

1

+

C

1

3

D

1

–

C

4

S

Y

N

C

4

5

A

V

D

4

6

A

V

D

4

7

V

I

N

–

C

4

8

V

I

N

+

C

4

3

V

C

M

4

2

V

R

E

F

4

1

S

E

N

S

E

4

0

R

B

I

A

S

3

9

A

V

D

3

8

V

I

N

–

B

3

7

V

I

N

+

B

25

D0+D

26

D0–D

27

D1+D

28

D1–D

29

DRVDD

30

AVDD

31

CLK+

32

CLK–

33

AVDD

34

AVDD

35

VIN–D

36

VIN+D

8

DRVDD

9

D0+A

10

D0–A

11

D1+A

12

D1–A

10065-007

AD9253-EP

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.

THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR

PROPER OPERATION.

Preliminary Technical Data AD9253-EP

Rev. PrA | Page 9 of 12

Pin No. Mnemonic Description

30

SCLK/DTP SPI Clock Input/Digital Test Pattern.

31

SDIO/OLM SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.

32

CSB SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.

33

PDWN Digital Input, 30 kΩ Internal Pull-Down.

PDWN high = power-down device.

PDWN low = run device, normal operation.

35 VIN−A ADC A Analog Input Complement.

36

VIN+A ADC A Analog Input True.

37

VIN+B ADC B Analog Input True.

38 VIN−B ADC B Analog Input Complement.

40

RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

41

SENSE Reference Mode Selection.

42

VREF Voltage Reference Input and Output.

43

VCM Analog Input Common-Mode Voltage.

44

SYNC Digital Input. SYNC input to clock divider.

47

VIN−C ADC C Analog Input Complement.

48

VIN+C ADC C Analog Input True.

AD9253TCPZR7-125EP

AD9253TCPZR7-125EP

Products related to this Datasheet