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AD9253TCPZR7-125EP

P1-P3P4-P6P7-P9P10-P12
AD9253-EP Preliminary Technical Data
Rev. PrA | Page 4 of 12
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter
1
Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz 25°C 75.3 dBFS
f
IN
= 30.5 MHz 25°C 75.2 dBFS
f
IN
= 70 MHz Full 72 74.1 dBFS
f
IN
= 140 MHz 25°C 72.2 dBFS
f
IN
= 200 MHz 25°C 70.7 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
f
IN
= 9.7 MHz 25°C 75.2 dBFS
f
IN
= 30.5 MHz 25°C 75.1 dBFS
f
IN
= 70 MHz Full 71.7 74.0 dBFS
f
IN
= 140 MHz 25°C 71.9 dBFS
f
IN
= 200 MHz 25°C 70.4 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz 25°C 12.2 Bits
f
IN
= 30.5 MHz 25°C 12.2 Bits
f
IN
= 70 MHz Full 12.0 Bits
f
IN
= 140 MHz 25°C 11.7 Bits
f
IN
= 200 MHz 25°C 11.4 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz 25°C 98 dBc
f
IN
= 30.5 MHz 25°C 92 dBc
f
IN
= 70 MHz Full 76 90 dBc
f
IN
= 140 MHz 25°C 85 dBc
f
IN
= 200 MHz 25°C 83 dBc
WORST HARMONIC (SECOND OR THIRD)
f
IN
= 9.7 MHz 25°C −98 dBc
f
IN
= 30.5 MHz 25°C −92 dBc
f
IN
= 70 MHz Full −90 −76 dBc
f
IN
= 140 MHz 25°C −85 dBc
f
IN
= 200 MHz 25°C −83 dBc
WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD)
f
IN
= 9.7 MHz 25°C −101 dBFS
f
IN
= 30.5 MHz 25°C −100 dBFS
f
IN
= 70 MHz Full −95 −83 dBFS
f
IN
= 140 MHz 25°C −96 dBFS
f
IN
= 200 MHz 25°C −92 dBFS
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
f
IN1
= 70.5 MHz, f
IN2
= 72.5 MHz 25°C 86 dBc
CROSSTALK
2
Full −95 dB
CROSSTALK (OVERRANGE CONDITION)
3
25°C −89 dB
POWER SUPPLY REJECTION RATIO (PSRR)
4
AVDD 25°C 48 dB
DRVDD 25°C 75 dB
ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Crosstalk is measured at 70 MHz with an −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3
The overrange condition is specified with 3 dB of the full-scale input range.
4
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
Preliminary Technical Data AD9253-EP
Rev. PrA | Page 5 of 12
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter
1
Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (SDIO/OLM)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF
LOGIC OUTPUT (SDIO/OLM)
3
Logic 1 Voltage (I
OH
= 800 A) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 µA) Full 0.05 V
DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 290 345 400 mV
Output Offset Voltage (V
OS
) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement
DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage (V
OD
) Full 160 200 230 mV
Output Offset Voltage (V
OS
) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/OLM pins sharing the same connection.
AD9253-EP Preliminary Technical Data
Rev. PrA | Page 6 of 12
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
1, 2
Temp Min Typ Max Unit
CLOCK
3
Input Clock Rate Full 10 1000 MHz
Conversion Rate Full 10 125 MSPS
Clock Pulse Width High (t
EH
) Full 4.00 ns
Clock Pulse Width Low (t
EL
) Full 4.00 ns
OUTPUT PARAMETERS
3
Propagation Delay (t
PD
) Full 2.3 ns
Rise Time (t
R
) (20% to 80%) Full 300 ps
Fall Time (t
F
) (20% to 80%) Full 300 ps
FCO Propagation Delay (t
FCO
) Full 1.5 2.3 3.1 ns
DCO Propagation Delay (t
CPD
)
4
Full t
FCO
+ (t
SAMPLE
/16) ns
DCO-to-Data Delay (t
DATA
)
4
Full (t
SAMPLE
/16) − 300 (t
SAMPLE
/16) (t
SAMPLE
/16) + 300 ps
DCO-to-FCO Delay (t
FRAME
)
4
Full (t
SAMPLE
/16) − 300 (t
SAMPLE
/16) (t
SAMPLE
/16) + 300 ps
Lane Delay (t
LD
) 90 ps
Data to Data Skew (t
DATA-MAX
− t
DATA-MIN
) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 250 ns
Wake-Up Time (Power-Down)
5
25°C 375 s
Pipeline Latency Full 16 Clock cycles
APERTURE
Aperture Delay (t
A
) 25°C 1 ns
Aperture Uncertainty (Jitter, t
J
) 25°C 135 fs rms
Out-of-Range Recovery Time 25°C 1 Clock cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4
t
SAMPLE
/16 is based on the number of bits in two LVDS data lanes. t
SAMPLE
= 1/f
S
.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
P1-P3P4-P6P7-P9P10-P12

AD9253TCPZR7-125EP

Mfr. #:
Buy AD9253TCPZR7-125EP
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 14 Bit 125Msps Quad
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