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NTEGRATED
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IRCUITS
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IVISION
NCD2100
12 www.ixysic.com R02
3.5 Operating Modes
The NCD2100 functions in one of two different operating modes. The load capacitance presented at pin X1 can be
controlled by the value loaded into the NCD2100 shift register, or by reading the value stored in the device’s internal
non-volatile memory.
By default the NCD2100 operates in Memory Mode so that in most end-user applications the capacitance value
corresponds to the calibration information programmed in the memory.
Whether shift register or memory mode is in use is determined by the logical state at the CLK input.
• CLK = 1: Shift Register Mode • CLK = 0: Memory Mode
3.5.1 Shift Register Mode
Shift Register Mode provides the means to alter the
load capacitance at any time. This mode varies from
the Memory Mode in that the value loaded into the
shift register is volatile and will be lost whenever power
to the device is removed.
Because Shift Register Mode is functional over the
entire operational range of the NCD2100, the
capacitance presented at pin X1 can be modified
under all allowable operating conditions.
Modifying the capacitance is easily accomplished by
loading the 11 bit control code into pin DA using the
clock (CLK), with pin PV held low or left open. When
pin PV is open circuit, an internal pull down resistor
having a nominal value of 180k will satisfy the logic 0
requirement.
The NCD2100 utilizes a first-in first-out shift register so
it is necessary to ensure only 11 rising edges of the
clock are applied to the device when entering data.
The least significant bit (LSB) of the serial data is the
first bit entered into the shift register. This bit is CHK
and does not affect the value of the capacitance. As
such, bit CHK is a “Don’t Care” in Shift Register Mode
and may be set to either a logic 0 or a logic 1.
When the last bit is entered into the shift register, the
CLK input must remain at a logic 1 for the control data
in the shift register to regulate the capacitor value.
Should the clock return to zero and then be pulled
back up to a logic 1, the value on DA when CLK
transitions to a logic 1 will be loaded into the MSB of
the shift register causing the contents in bits 11:1 to
shift into locations 10:0. generally resulting in an
incorrect control code.
3.5.2 Memory Mode
Memory Mode is the default mode of operation as this
is the most likely in-service condition for a typical
application in a finished product. This operational
mode uses the value stored in the non-volatile
memory to configure the capacitor to the proper value.
To facilitate Memory Mode as the default mode, an
internal pull down resistor at the CLK pin with a
nominal value of 135k. provides the required logic 0
state.
In addition to the internal pull down resistor at the CLK
pin there are pull down resistors at the DA and PV pins
to maintain inert logic 0 states at these inputs ensuring
stable and predictable behavior without the need for
supplementary external discrete components. The
nominal value of the pull down resistor at the DA input
is 135k and the nominal value at PV is 180k.
To use Memory Mode, the non-volatile memory within
the NCD2100 must be programmed with the
appropriate digital code to create the desired
capacitive value at the X1 pin.
