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4.2.2 Single-Bit Programming Mode (CHK=0)
In Single-Bit Programming Mode, the memory
functions as a fuse. This means that once the memory
bits have programmed to a logic 1 they can not be
cleared using this programming mode.
The detailed sequence for single-bit programming of
the memory is:
1. Determine the desired capacitance value.
2. Apply the programming conditions listed in
Section 3.7.1 "Memory Programming
Conditions” on page 13.
3. Erase the memory content if it is not already
erased (see “Erasing the Memory” on
page 17).
4. Verify the memory content (see “Programming
Verification” on page 17).
5. Send the programming sequence to program
one bit (see example depicted in Figure 6).
6. After a 4s delay, the voltage at PV pin must be
set to +6.5V±0.5V for between 40ms and 80ms.
7. Repeat steps 5 & 6 for each additional memory
bit that needs be set to a logic 1.
8. Verify the memory content (see “Programming
Verification” on page 17).
The CHK bit is always read as logic 1 during
program verification.
For this example, CDAC2 BIT2 needs to be set to a
logic 1. Depicted in Figure 6 CDAC2 BIT2 is being
programmed to a logic 1 in memory by loading a
logic 0 into that bit’s address in the shift register while
all of the remaining bits in the shift register are set to
logic 1. CLK loads the entire sequence of these bits
into the shift register and when the last bit is loaded
CLK must remain high. After a minimum wait of 4s,
set the PV pin to +6.5V±0.5V for between 40ms and
80ms to store a logic 1 into the selected EEPROM bit
(in this example CDAC2 BIT2).
Should one or more memory bits need to be returned
to a logic 0 the other programming mode, All-Bits
Mode, can be used to make the changes.
Figure 6: Single-Bit Programming Sequence
CLK
DA
PV
4µs
40ms
0 t
time
CHK
CDAC3 CDAC2 CDAC1
BIT1 BIT2 BIT3 BIT4 BIT5 BIT1 BIT2 BIT3 BIT1 BIT2
6.5V ± 0.5V
