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AT17LV512-10CI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
7
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
3. Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE
and CE pins control the tri-state buffer on the DATA
output pin and enable the address counter. When RESET/OE
is driven High, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the
output of the AT17LV series configurator. If CE
is held High after the RESET/OE reset pulse, the
counter is disabled and the DATA output pin is tri-stated. When OE
is subsequently driven Low,
the counter and the DATA output pin are enabled. When RESET/OE
is driven High again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE
.
When the configurator has driven out all of its data and CEO
is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET
/OE.
Note: 1. The CEO feature is not available on the AT17LV65 device.
4. Pin Description
Name I/O
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010 AT17LV002 AT17LV040
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
8
DIP/
LAP
20
PLCC
20
SOIC
8
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
44
PLCC
44
TQFP
44
PLCC
44
TQFP
DATAI/O122121121240240
CLKI244243243543543
WP1I––––5––5–––––
RESET/
O
E
I36636836819131913
WP2I –7––7–––––
CE
I 4 8 8 4 8 10 4 8 10 21 15 21 15
GND 51010510115101124182418
CEO
O
61414614
13
614
13
27 21 27 21
A2 I – –
READYO––––15––15–29232923
SER_EN
I71717717187171841354135
V
CC
82020820208202044384438
8
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
4.1 DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2 CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
4.3 WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
4.4 RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET
/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE
or
RESET
/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET
/OE.
4.5 WP
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP
is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on AT17LV65/128/256 devices.
4.6 WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010 devices.
4.7 CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE
disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
Low).
4.8 GND
Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
4.9 CEO
Chip Enable Output (active Low). This output goes Low when the address counter has reached
its maximum value. In a daisy chain of AT17LV series devices, the CEO
pin of one device must
be connected to the CE
input of the next device in the chain. It will stay Low as long as CE is
Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO
will stay High until
the entire EEPROM is read again. This CEO
feature is not available on the AT17LV65 device.
9
2321H–CNFG–03/06
AT17LV65/128/256/512/010/002/040
4.10 A2
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN
is Low). A2 has an internal pull-down resistor.
4.11 READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
4.12 SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN
should be
tied to V
CC
.
4.13 V
CC
3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17LV Serial Configuration EEPROM has
been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
6. Control of Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and
self-explanatory.
• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.
•The CEO
output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
• SER_EN
must be connected to V
CC
(except during ISP).
• The READY
(1)
pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Note: 1. This pin is not available for the AT17LV65/128/256 devices.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AT17LV512-10CI

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Buy AT17LV512-10CI
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Configuration Memory ASICS
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