TDA8922CJ/N1,112 Datasheet TDA8922CJ/N1,112, TDA8922CTH/N1,118, TDA8922CTH/N1,112 | P10-P12

Product data sheet Rev. 01 — 7 September 2009 10 of 40

NXP Semiconductors

TDA8922C

2 × 75 W class-D power ampliﬁer

• Short-circuit impedance < Z

: the ampliﬁer limits the maximum output current to I

ORM

and at the same time discharges the capacitor on pin PROT. When C

PROT

is fully

discharged, the ampliﬁer shuts down completely and an internal timer is started.

The value of the protection capacitor (C

PROT

) connected to pin PROT can be between

10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is

enabled that will discharge C

PROT

When OCP is activated, the active power transistor is turned off and the other power

transistor is turned on to reduce the current (C

PROT

is partially discharged). Normal

operation is resumed at the next switching cycle (C

PROT

is recharged). C

PROT

is partially

discharge each time OCP is activated during a switching cycle. If the fault condition that

caused OCP to be activated persists long enough to fully discharge C

PROT

, the ampliﬁer

will switch off completely and a restart sequence will be initiated.

After a ﬁxed period of 100 ms, the ampliﬁer will attempt to switch on again, but will fail if

the output current still exceeds the OCP threshold. The ampliﬁer will continue trying to

switch on every 100 ms. The average power dissipation will be low in this situation

because the duty cycle is short.

Switching the ampliﬁer on and off in this way will generate unwanted ‘audio holes’. This

can be avoided by increasing the value of C

PROT

(up to 220 pF) to delay ampliﬁer

switch-off. C

PROT

will also prevent the ampliﬁer switching off due to transient

frequency-dependent impedance drops at the speakers.

The ampliﬁer will switch on, and remain in Operating mode, once the overcurrent

condition has been removed. OCP ensures the TDA8922C ampliﬁer is fully protected

against short-circuit conditions while avoiding audio holes.

[1] Tested using three samples and an external clock.

8.3.3 Window Protection (WP)

Window Protection (WP) checks the conditions at the output terminals of the power stage

and is activated:

• During the start-up sequence, when the TDA8922C is switching from Standby to

Mute.

Table 4. Current limiting behavior during low output impedance conditions at different

values of C

PROT

[1]

Type V

(V)

(mV, p-p) f (Hz) C

PROT

(pF) PWM output stops

Short

=0Ω)

Short

= 0.5 Ω)

Short

=1Ω)

TDA8922C +29.5/

−29.5

500 20 10 yes yes yes

1000 10 yes yes yes

20 15 yes yes yes

1000 15 yes no no

1000 220 no no no

Product data sheet Rev. 01 — 7 September 2009 11 of 40

NXP Semiconductors

TDA8922C

2 × 75 W class-D power ampliﬁer

Start-up will be interrupted If a short-circuit is detected between one of the output

terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8922C will wait until the

short-circuit to the supply lines has been removed before resuming start-up. The short

circuit will not generate large currents because the short-circuit check is carried out

before the power stages are enabled.

• When the ampliﬁer is shut down completely because the OCP circuit has detected a

short circuit to one of the supply lines.

WP will be activated when the ampliﬁer attempts to restart after 100 ms (see

Section 8.3.2). The ampliﬁer will not start-up again until the short circuit to the supply

lines has been removed.

8.3.4 Supply voltage protection

If the supply voltage drops below the minimum supply voltage threshold, V

th(uvp)

, the UVP

circuit will be activated and the system will shut down. Once the supply voltage rises

above V

th(uvp)

again, the system will restart after a delay of 100 ms.

If the supply voltage exceeds the maximum supply voltage threshold, V

th(ovp)

, the OVP

circuit will be activated and the power stages will be shut down. When the supply voltage

drops below V

th(ovp)

again, the system will restart after a delay of 100 ms.

An additional UnBalance Protection (UBP) circuit compares the positive analog supply

voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is

triggered if the voltage difference exceeds a factor of two (V

DDA

> 2 ×|V

SSA

| OR |V

SSA

| >

2 × V

DDA

). When the supply voltage difference drops below the unbalance threshold,

th(ubp)

, the system restarts after 100 ms.

An overview of all protection circuits and their respective effects on the output signal is

provided in Table 5.

[1] Ampliﬁer gain depends on the junction temperature and heatsink size.

[2] The ampliﬁer shuts down completely only if the short-circuit impedance is below the impedance threshold

; see Section 8.3.2). In all other cases, current limiting results in a clipped output signal.

[3] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been

activated (short-circuit to one of the supply lines).

8.4 Differential audio inputs

The audio inputs are fully differential ensuring a high common mode rejection ratio and

maximum ﬂexibility in the application.

Table 5. Overview of TDA8922C protection circuits

Protection name Complete

shutdown

Restart directly Restart after

100 ms

Pin PROT

detection

TFB

[1]

NNNN

OTP Y N Y N

OCP Y

[2]

WP N

[3]

YNN

UVPYNYN

OVP Y N Y N

UBPYNYN

Product data sheet Rev. 01 — 7 September 2009 12 of 40

NXP Semiconductors

TDA8922C

2 × 75 W class-D power ampliﬁer

• Stereo operation: to avoid acoustical phase differences, the inputs should be in

anti-phase and the speakers should be connected in anti-phase. This conﬁguration:

– minimizes power supply peak current

– minimizes supply pumping effects, especially at low audio frequencies

• Mono BTL operation: the inputs must be connected in anti-parallel. The output of one

channel is inverted and the speaker load is connected between the two outputs of the

TDA8922C. In practice (because of the OCP threshold) the output power can be

boosted to twice the output power that can be achieved with the single-ended

conﬁguration.

The input conﬁguration for a mono BTL application is illustrated in Figure 7.

9. Limiting values

Fig 7. Input conﬁguration for mono BTL application

IN1P

OUT1

power stage

mbl466

OUT2

SGND

IN1M

IN2P

IN2M

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

∆V voltage difference V

− V

; Standby, Mute modes - 65 V

ORM

repetitive peak output current maximum output current limiting 6 - A

stg

storage temperature −55 +150 °C

amb

ambient temperature −40 +85 °C

junction temperature - 150 °C

MODE

voltage on pin MODE referenced to SGND 0 6 V

OSC

voltage on pin OSC 0 SGND + 6 V

input voltage referenced to SGND

pins IN1P, IN1M, IN2P and IN2M

−5+5 V

PROT

voltage on pin PROT referenced to voltage on pin VSSD 0 12 V

ESD

electrostatic discharge voltage Human Body Model (HBM) −2000 +2000 V

Charged Device Model (CDM) −500 +500 V

q(tot)

total quiescent current Operating mode; no load; no ﬁlter

no RC-snubber network connected

-70 mA

PWM(p-p)

peak-to-peak PWM voltage on pins OUT1 and OUT2 - 120 V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P40

TDA8922CJ/N1,112

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TDA8922CJ/N1,112

TDA8922CJ/N1,112

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