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TDA8922CJ/N1,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
TDA8922C_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 7 September 2009 16 of 40
NXP Semiconductors
TDA8922C
2 × 75 W class-D power amplifier
[1] R
s(L)
is the series resistance of the low-pass LC filter inductor used in the application.
[2] Output power is measured indirectly; based on R
DSon
measurement; see Section 13.3.
[3] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested.
[4] V
ripple
= V
ripple(max)
= 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[5] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[7] P
o
= 1 W; f
i
= 1 kHz.
[8] V
i
= V
i(max)
= 1 V (RMS); f
i
= 1 kHz.
[9] Leads and bond wires included.
12.3 Mono BTL application characteristics
[1] R
s(L)
is the series resistance of the low-pass LC filter inductor used in the application.
[2] Output power is measured indirectly; based on R
DSon
measurement; see Section 13.3.
[3] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested.
[4] V
ripple
= V
ripple(max)
= 2 V (p-p).
[5] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter; low noise due to BD modulation.
[6] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter.
[7] V
i
= V
i(max)
= 1 V (RMS); f
i
= 1 kHz.
Table 11. Dynamic characteristics
V
DD
=25V; V
SS
=
−
25 V; R
L
= 8
Ω
; f
i
= 1 kHz; f
osc
= 350 kHz; R
s(L)
< 0.1
Ω
[1]
; T
amb
= 25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
P
o
output power T
j
=85°C; L
LC
=22µH; C
LC
= 680 nF
(see
Figure 10)
[2]
THD = 0.5 %; R
L
= 8 Ω - 115 - W
THD = 10 %; R
L
= 8 Ω - 155 - W
THD total harmonic distortion P
o
= 1 W; f
i
= 1 kHz
[3]
- 0.02 - %
P
o
= 1 W; f
i
= 6 kHz
[3]
- 0.05 - %
G
v(cl)
closed-loop voltage gain - 36 - dB
SVRR supply voltage rejection ratio between pin VDDPn and SGND
Operating mode; f
i
= 100 Hz
[4]
-72-dB
Operating mode; f
i
= 1 kHz
[4]
-64-dB
Mute mode; f
i
= 100 Hz
[4]
-86-dB
Standby mode; f
i
= 100 Hz
[4]
- 100 - dB
between pin VSSPn and SGND
Operating mode; f
i
= 100 Hz
[4]
-72-dB
Operating mode; f
i
= 1 kHz
[4]
-72-dB
Mute mode; f
i
= 100 Hz
[4]
-86-dB
Standby mode; f
i
= 100 Hz
[4]
- 100 - dB
Z
i
input impedance measured between one of the input
pins and SGND
45 63 - kΩ
V
n(o)
output noise voltage Operating mode; R
s
=0Ω
[5]
- 190 - µV
Mute mode
[6]
-45-µV
α
mute
mute attenuation f
i
= 1 kHz; V
i
= 2 V (RMS)
[7]
-75-dB
CMRR common mode rejection ratio V
i(CM)
= 1 V (RMS) - 75 - dB
TDA8922C_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 7 September 2009 17 of 40
NXP Semiconductors
TDA8922C
2 × 75 W class-D power amplifier
13. Application information
13.1 Mono BTL application
When using the power amplifier in a mono BTL application, the inputs of the two channels
must be connected in anti-parallel and the phase of one of the inputs must be inverted;
(see Figure 7). In principle, the loudspeaker can be connected between the outputs of the
two single-ended demodulation filters.
13.2 Pin MODE
To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE.
The bias-current setting of the VI converter input is directly related to the voltage on pin
MODE. In turn the bias-current setting of the VI converters is directly related to the DC
output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output
offset voltage, ensuring a pop noise-free transition between Mute and Operating modes. A
time-constant of 500 ms is sufficient to guarantee pop noise-free start-up; see Figure 4,
Figure 5 and Figure 8 for more information.
13.3 Estimating the output power
13.3.1 Single-Ended (SE)
Maximum output power:
(1)
Maximum output current is internally limited to 6 A:
(2)
Where:
• P
o(0.5 %)
: output power at the onset of clipping
• R
L
: load impedance
• R
DSon(hs)
: high-side R
DSon
of power stage output DMOS (temperature dependent)
• R
s(L)
: series impedance of the filter coil
• t
w(min)
: minimum pulse width (typical 100 ns, temperature dependent)
• f
osc
: oscillator frequency
Remark: Note that I
o(peak)
should be less than 6 A (Section 8.3.2). I
o(peak)
is the sum of the
current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
P
o 0.5%()
R
L
R
L
R
DSon hs()
R
sL()
++
--------------------------------------------------------
0.5 V
DD
V
SS
–()1t
w min()
0.5× f
osc
–()××
2
2R
L
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=
I
opeak()
0.5 V
DD
V
SS
–()1t
w min()
0.5 f
osc
×–()×
R
L
R
DSon hs()
R
sL()
++
------------------------------------------------------------------------------------------------------
=
TDA8922C_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 7 September 2009 18 of 40
NXP Semiconductors
TDA8922C
2 × 75 W class-D power amplifier
13.3.2 Bridge-Tied Load (BTL)
Maximum output power:
(3)
Maximum output current internally limited to 6 A:
(4)
Where:
• P
o(0.5 %)
: output power at the onset of clipping
• R
L
: load impedance
• R
DSon(hs)
: high-side R
DSon
of power stage output DMOS (temperature dependent)
• R
DSon(ls)
: low-side R
DSon
of power stage output DMOS (temperature dependent)
• R
s(L)
: series impedance of the filter coil
• V
P
: single-sided supply voltage or 0.5 × (V
DD
+ |V
SS
|)
• t
w(min)
: minimum pulse width (typical 100 ns, temperature dependent)
• f
osc
: oscillator frequency
Remark: Note that I
o(peak)
should be less than 6 A; see Section 8.3.2.I
o(peak)
is the sum of
the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
13.4 External clock
To ensure duty cycle-independent operation, the external clock frequency is divided by
two internally. The external clock frequency is therefore twice the internal clock frequency
(typically 2 × 350 kHz = 700 kHz).
If several Class D amplifiers are used in a single application, it is recommended that all
the devices run at the same switching frequency. This can be achieved by connecting the
OSC pins together and feeding them from an external oscillator. When using an external
oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the
internal oscillator and causes the PWM to switch at half the external clock frequency.
The internal oscillator requires an external resistor R
OSC
, connected between pin OSC
and pin VSSA. R
OSC
must be removed when using an external oscillator.
The noise generated by the internal oscillator is supply voltage dependent. An external
low-noise oscillator is recommended for low-noise applications running at high supply
voltages.
13.5 Heatsink requirements
An external heatsink must be connected to the TDA8922C.
P
o 0.5%()
R
L
R
L
R
DSon hs()
R
DSon ls()
++
-------------------------------------------------------------------
V
DD
V
SS
–()1t
w min()
0.5 f
osc
×–()××
2
2R
L
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=
I
opeak()
V
DD
V
SS
–()1t
w min()
0.5 f
osc
×–()×
R
L
R
DSon hs()
R
DSon ls()
+()2R
sL()
++
-----------------------------------------------------------------------------------------------
=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA8922CJ/N1,112

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Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers 1CH Mono/2CH Stereo Audio Amp Speaker
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