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LTC1266CS-3.3#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
10
LTC1266
LTC1266 -3.3/LTC1266 -5
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode
operation to be falsely
triggered. Do not allow the core to saturate!
Kool Mµ is a very good, low loss core material for toroids,
with a “soft” saturation characteristic. Molypermalloy is
slightly more efficient at high (>200kHz) switching fre-
quency. Toroids are very space efficient, especially when
you can use several layers of wire. Because they generally
lack a bobbin, mounting is more difficult. However, new
designs for surface mount are available from Coiltronics
and Beckman Industrial Corp. which do not increase the
height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1266 series: either a P-channel MOSFET or an
N-channel MOSFET for the main switch and an N-channel
MOSFET for the synchronous switch. The main selection
criteria for the power MOSFETs are the type of MOSFET,
threshold voltage V
GS(TH)
and on-resistance R
DS(ON)
.
The cost and maximum output current determine the type
of MOSFET for the topside switch. N-channel MOSFETs
have the advantage of lower cost and lower R
DS(ON)
at the
expense of slightly increased circuit complexity. For lower
current applications where the losses due to R
DS(ON)
are
small, a P-channel MOSFET is recommended due to the
lower circuit complexity. However, at load currents in
excess of 3A where the R
DS(ON)
becomes a significant
portion of the total power loss, an N-channel is strongly
recommended to maximize efficiency.
The maximum output current I
MAX
determines the R
DS(ON)
requirement for the two MOSFETs. When the LTC1266
series is operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is
always conducting the average load current. The duty
cycles for the two MOSFETs are given by:
Topside Duty Cycle =
V
OUT
V
IN
Bottom-Side Duty Cycle =
V
IN
– V
OUT
V
IN
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations). The complete expression for operating
frequency of the circuit in Figure 1 is given by:
f =
1
t
OFF
)
)
1 –
V
OUT
V
IN
where:
t
OFF
= 1.3 • 10
4
• C
T
•
)
)
V
REG
V
OUT
V
REG
is the desired output voltage (i.e., 5V, 3.3V). V
OUT
is the
measured output voltage. Thus V
REG
/V
OUT
= 1 in regulation.
Once the frequency has been set by C
T
, the inductor L
must be chosen to provide no more than 25mV/R
SENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
L
MIN
= 5.1 • 10
5
• R
SENSE
• C
T
• V
REG
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductor is used, the inductor current will decrease past
zero and change polarity.
A consequence of this is that
the LTC1266 series may not enter Burst Mode
operation
and efficiency will be slightly degraded at low currents.
Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, Kool Mµ
®
on molypermalloy (MPP)
cores. Lower cost powdered iron cores provide suitable
performance but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing satura-
tion. Ferrite core material saturates “hard,” which means
that inductance collapses abruptly when the peak design
Kool Mµ
is a registered trademark of Magnetics, Inc.
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LTC1266
LTC1266-3.3/LTC1266-5
From the duty cycles, the required R
DS(ON)
for each
MOSFET can be derived:
TS R
DS(ON)
=
V
IN
• P
T
V
OUT
• I
MAX
2
• (1 + δ
T
)
BS R
DS(ON)
=
V
IN
• P
B
(V
IN
– V
OUT
) • I
MAX
2
• (1 + δ
B
)
where P
T
and P
B
are the allowable power dissipations and
δ
T
and δ
B
are the temperature dependencies of R
DS(ON)
. P
T
and P
B
will be determined by efficiency and/or thermal
requirements (see Efficiency Considerations). For a MOSFET,
(1 + δ) is generally given in the form of a normalized
R
DS(ON)
vs temperature curve, but δ
PCH
= 0.007/°C and
δ
NCH
= 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be used.
For V
IN
> 8V, standard threshold MOSFETs (V
GS(TH)
< 4V)
may be used. If V
IN
is expected to drop below 8V, logic-
level threshold MOSFETs (V
GS(TH)
< 2.5V) are strongly
recommended. The LTC1266 series Power V
IN
must al-
ways be less than the absolute maximum V
GS
ratings for
the MOSFETs.
The Schottky diode D1 shown in Figure 1 only conducts
during the deadtime between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the bottom-side MOSFET from turning on
and storing charge during the deadtime, which could cost
as much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting I
MAX
.
C
IN
and C
OUT
Selection
In continuous mode, the current through the topside
MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR (Effective
Series Resistance) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
C
IN
Required I
RMS
≈ I
MAX
[V
OUT
(V
IN
–
V
OUT
)]
1/2
V
IN
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Always consult the
manufacturer if there is any question. An additional 0.1µF
to 1µF ceramic capacitor is also required on Power V
IN
(Pin 2) for high frequency decoupling.
The selection of C
OUT
is driven by the required ESR.
The
ESR of C
OUT
must be less than twice the value of R
SENSE
for proper operation of the LTC1266 series:
C
OUT
Required ESR < 2R
SENSE
Optimum efficiency is obtained by making the ESR equal
to R
SENSE
. As the ESR is increased up to 2R
SENSE
, the
efficiency degrades by less than 1%. If the ESR is greater
than 2R
SENSE
, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode
operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent. If Burst Mode operation is dis-
abled, the ESR requirement can be relaxed and is limited
only by the allowable output voltage ripple.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for C
OUT
has been met, the RMS current
rating generally far exceeds the I
RIPPLE(P-P)
requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirements of the application. An
excellent choice is the AVX TPS series of surface mount
tantalums.
At low supply voltages, a minimum capacitance at C
OUT
is needed to prevent an abnormal low frequency oper-
ating mode (see Figure 4). When C
OUT
is made too
small, the output ripple at low frequencies will be large
enough to trip the voltage comparator. This causes
Burst Mode
operation to be activated when the LTC1266
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LTC1266
LTC1266 -3.3/LTC1266 -5
Driving N-Channel Topside MOSFETs
Driving an N-channel topside MOSFET (PINV, Pin 3, tied to
PWR V
IN
) is a little trickier than driving a P-channel since
the gate voltage must be positive with respect to the
source to turn it on, which means that the gate voltage
must be higher than V
IN
. This requires either a second
supply at least V
GS(ON)
above V
IN
or a bootstrapping circuit
to boost the V
IN
to the proper level. The easiest method is
using a higher supply (see Figure 14) but if one is not
available, the bootstrap method can be used at the ex-
pense of an additional diode (see Figure 1). The bootstrap
works by charging the bootstrap capacitor to V
IN
during
the off-time. During the on-time, the bottom plate of the
capacitor is pulled up to V
IN
so that the voltage at Pin 2 is
now twice V
IN
(plus any ringing on the switch node).
Since the maximum allowable voltage at Pin 2 is 20V, the
Figure 1 bootstrap circuit limits V
IN
to less than 10V. A
higher V
IN
can be achieved if the bootstrap capacitor is
charged to a voltage less than V
IN
, in which case
V
IN(MAX)
␣ = 20 – V
CAP
.
N-channel mode, internal circuitry limits the maximum
on-time to 60µs to guarantee start-up of the bootstrap
circuit. This maximum on-time reduces the maximum
duty cycle to:
Max Duty Cycle =
60µs
60µs + t
OFF
which slightly increases the minimum input voltage at
which dropout occurs. However, because of the superior
on-conductance of the N-channel, the dropout perfor-
mance of an all N-channel regulator is still better (see
Figure 5) even with the duty cycle limitation, except at light
loads.
Low-Battery Comparator
The LTC1266 has an on-chip low-battery comparator
which can be used to sense a low-battery condition when
implemented as shown in Figure 6. The resistor divider
R1, R2 sets the comparator trip point as follows:
V
TRIP
= 1.25
)
)
1 +
R2
R1
(V
IN
– V
OUT
) VOLTAGE (V)
0
C
OUT
(µF)
600
800
1000
4
1266 F04
400
200
0
1
2
3
5
L = 50µH
R
SENSE
= 0.02Ω
L = 25µH
R
SENSE
= 0.02Ω
L = 50µH
R
SENSE
= 0.05Ω
Figure 4. Minimum Value of C
OUT
series would normally be in continuous operation. The
output remains in regulation at all times. This minimum
capacitance requirement may be relaxed if Burst Mode
operation is disabled.
N-Channel vs P-Channel MOSFETs
The LTC1266 has the capability to drive either an
N-channel or a P-channel topside switch to give the user
more flexibility. N-channel MOSFETs are superior in per-
formance to P-channel due to their lower R
DS(ON)
and
lower gate capacitance and are typically less expensive;
however, they do have a slightly more complicated gate
drive requirement and a more limited input voltage range
(see following sections).
Driving P-Channel Topside MOSFETs
The P-channel topside switch circuit configuration is the
most straightforward due to the requirement of only one
supply voltage level. This is due to the negative gate
threshold of the P-channel MOSFET which allows the
MOSFET to be switched on and off by swinging the gate
between V
IN
and ground. The phase invert (Pin 3) is tied
to ground to choose this operating mode. Normally, the
converter input (V
IN
) is connected to the LTC1266 supply
Pins 2 and 5 and can go as high as 20V. Pin 2 supplies the
high frequency current pulses to switch the MOSFETs and
should be decoupled with a 0.1µF to 1µF ceramic capaci-
tor. Pin 5 supplies most of the quiescent power to the rest
of the chip.
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LTC1266CS-3.3#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Syn Switching Reg Controller
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