10
LTC1343
APPLICATIONS INFORMATION
WUU
U
will configure the port for DCE mode when high, and DTE
when low.
The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon-
nected (1) or wired to ground (0) in the cable as shown in
Figure 11.
The pull-up resistors R1 through R4 will ensure a binary
1 when a pin is left unconnected and that the two LTC1343s
and the LTC1344 enter the no-cable mode when the cable
is removed. In the no-cable mode the LTC1343 supply
current drops to less than 200µA and all LTC1343 driver
outputs and LTC1344 resistive terminations are forced
into a high impedance state. Note that the data latch pin,
LATCH, is shorted to ground for all chips.
The interface protocol may also be selected by the serial
controller or host microprocessor as shown in Figure 12.
The mode selection pins M0, M1, M2 and DCE/DTE can be
shared between multiple interface ports, while each port
Figure 11: Single Port DCE/V.35 Mode Selection in the Cable
RL (Remote Loop-back) and RI (Ring Indicate). The
LTC1344 cable termination chip is used only for the clock
and data signals because they must support V.35 cable
termination. The control signals do not need any external
resistors.
Mode Selection
The interface protocol is selected using the mode select
pins M0, M1, M2 and CTRL/CLK (see the Mode Selection
table). The CTRL/CLK pin should be pulled high if the
LTC1343 is being used to generate control signals and
pulled low if used to generate clock and data signals.
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, CTRL/CLK = 1 and the drivers and
receivers will operate in RS232 (V.28) electrical mode. For
the clock and data signals, CTRL/CLK = 0 and the drivers
and receivers will operate in V.35 electrical mode, except
for the single-ended driver and receiver which will operate
in the RS232 (V.28) electrical mode. The DCE/DTE pin
NC
NC
CABLE
1343 F11
17
18
19
21
LTC1343
LTC1343
CONNECTOR
20
21
19
18
17
22
21
M2 M1
LTC1344
LATCH
M0 (DATA)
23 24 1
CTRL/CLK
22
(DATA)
M0
M1
M2
DCE/DTE
LATCH
20
CTRL/CLK
22
DCE/DTE
M2
M1
M0
(DATA)
LATCH
V
CC
DCE/
DTE
R1, 10k
V
CC
R2, 10k
V
CC
R3, 10k
V
CC
R4, 10k
V
CC
11
LTC1343
APPLICATIONS INFORMATION
WUU
U
Figure 12: Mode Selection by the Controller
has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
the chip.
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or V
CC
.
Cable Termination
Traditional implementations have included switching re-
sistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate termi-
nations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software con-
trol, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
protocols.
V.10 (RS423) Interface
A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con-
nected to A, and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.
Figure 14. V.10 Receiver Input Impedance
Figure 13. Typical V.10 Interface
1343 F12
CONTROLLER
PORT #3
M0
M1
M2
DCE/DTE
LATCH 1
LATCH 2
LATCH 3
M0
M1
M2
DCE/DTE
LATCH
PORT #2
M0
M1
M2
DCE/DTE
LATCH
PORT #1
M0
M1
M2
DCE/DTE
LATCH
CONNECTOR #1CONNECTOR #2CONNECTOR #3
AA
'
CB
'
C
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
1343 F13
I
Z
V
Z
–10V
–3.25mA
3.25mA
–3V
3V 10V
1343 F14
12
LTC1343
APPLICATIONS INFORMATION
WUU
U
The V.10 receiver configuration in the LTC1343 and
LTC1344 is shown in Figure 15. In V.10 mode switches S1
and S2 inside the LTC1344 and S3 inside the LTC1343 are
turned off. Switch S4 inside the LTC1343 shorts the
noninverting receiver input to ground so the B input at the
connector can be left floating. The cable termination is
then the 30k input impedance to ground of the LTC1343
V.10 receiver.
V.11 (RS422) Interface
A typical V.11 balanced interface is shown in Figure 16. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is required
to prevent reflections from corrupting the data. The re-
ceiver inputs must also be compliant with the impedance
curve shown in Figure 14.
In V.11 mode, all switches are off except S1 inside the
LTC1344 which connects a 103 differential termination
impedance to the cable as shown in Figure 17.
V.28 (RS232) Interface
A typical V.28 unbalanced interface is shown in Figure 18.
A. V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with inputs A' con-
nected to A, ground C' connected via the signal return
ground C.
In V.28 mode all switches are off except S3 inside the
LTC1343 which connects a 6k (R8) impedance to ground
in parallel with 20k (R5) plus 10k (R6) for a combined
impedance of 5k as shown in Figure 19. The noninverting
input is disconnected inside the LTC1343 receiver and
connected to a TTL level reference voltage for a 1.4V
receiver trip point.
Figure 17. V.11 Receiver Configuration
Figure 15. V.10 Receiver Configuration
Figure 18. Typical V.28 Interface
Figure 16. Typical V.11 Interface
R3
124
R5
20k
LTC1344
LTC1343
RECEIVER
1343 F15
A
B
A
'
B'
C'
R1
51.5
R8
6k
S1
S2
S3
S4
R2
51.5
R6
10k
R7
10k
GND
R4
20k
AA'
B
C
B'
C'
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
100
MIN
1343 F16
R3
124
R5
20k
LTC1344
LTC1343
RECEIVER
1343 F17
A
B
A
'
B'
C'
R1
51.5
R8
6k
S2
S3
S4
R2
51.5
R6
10k
R7
10k
GND
R4
20k
S1
AA
'
CC
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
1343 F18

LTC1343IGW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-232 Interface IC Sftwr-Sel Multiprotocol Tran
Lifecycle:
New from this manufacturer.
Delivery:
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