13
LTC1343
APPLICATIONS INFORMATION
WUU
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Figure 19. V.28 Receiver Configuration
Figure 21. V.35 Receiver Configuration
The generator differential impedance must be 50 to
150 and the impedance between shorted terminals (A
and B) and ground C must be 150 ±15. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 22.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
V.35 Interface
A typical V.35 balanced interface is shown in Figure 20. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100±10, and the impedance between shorted termi-
nals (A' and B) and ground C' must be 150 ±15.
In V.35 mode, both switches S1 and S2 inside the LTC1344
are on, connecting the T network impedance as shown in
Figure 21. Both switches in the LTC1343 are off. The 30k
input impedance of the receiver is placed in parallel with
the T network termination, but does not affect the overall
input impedance significantly.
Figure 20. Typical V.35 Interface
Figure 22. V.35 Driver Using the LTC1344
R3
124
R5
20k
LTC1344
LTC1343
RECEIVER
1343 F19
A
B
A
'
B
'
C
'
R1
51.5
R8
6k
S2
S3
S4
R2
51.5
R6
10k
R7
10k
GND
R4
20k
S1
R3
124
R5
20k
LTC1344
LTC1343
RECEIVER
1343 F21
A
B
A
'
B
'
C
'
R1
51.5
R8
6k
S2
S3
S4
R2
51.5
R6
10k
R7
10k
GND
R4
20k
S1
A
A
'
B
C
B
'
C
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
1343 F20
50
125
50
50
125
50
V.35 DRIVER
A
B
C
51.5
S2
ON
S1
ON
1343 F22
51.5
LTC1344
124
C1
100pF
14
LTC1343
APPLICATIONS INFORMATION
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Echoed Clock Mode
The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configured as an input. On the DCE side, the transmit clock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.
Loop-Back
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.
If the echoed clock mode is selected by pulling EC low, D3
becomes an output and is connected to receiver 2’s output
R3 in DTE mode as shown in Figure 26. In the echoed clock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.
Figure 23. EIA-530 Echoed Clock Configuration
LTC1343
DCEDTE
LTC1343LTC1344
LTC1344
1343 F23
D1
D4
D4
D3
D2
R1
R4
103
103
103
103
103
R3
LL
TXD
TXC
INVERT
RXC
RXD
TM
SERIAL
CONTROLLER
R3
R2
R1
R4
D3
D2
D1
LL
RXD
RXC
INVERT
TXC
TXD
TM
SERIAL
CONTROLLER
R2
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
M0
M1
M2
DCE/DTE
LATCH
1 0 1 0 0 1 0 0
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
1 0 1 0 1 1 0 01 0 1 0 0
M0
M1
M2
DCE/DTE
LATCH
1 0 1 1 0
LL
TXD
SCTE
TXC
RXC
RXD
TM
15
LTC1343
Figure 24. Normal DTE Loop-Back
Figure 25. Normal DCE Loop-Back
APPLICATIONS INFORMATION
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LTC1343 LTC1344
1343 F24
D1
D4
D3
D2
R1
R4
103
103
103
R3
LL
TXD
SCTE
TXC
RXC
RXD
TM
SERIAL
CONTROLLER
R2
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
M0
M1
M2
DCE/DTE
LATCH
1 0 1 0 0 0 1 0 1 0 1 0 0
LL
TXD
SCTE
RXD
LTC1343
D1
D4
D3
D2
R1
R4
R3
RL
RTS
DTR
DCD
DSR
CTS
RI
R2
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
1 0 1 1 0 0 1 0
DCD
DSR
CTS
LTC1343
R4
D4
D3
D2
R1
D1
R3
R2
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
LTC1343LTC1344
1343 F25
R4
D4
D3
D2
R1
D1
103
103
R3
LL
TXD
SCTE
TXC
RXC
RXD
TM
SERIAL
CONTROLLER
R2
M0
M1
M2
DCE/DTE
LATCH
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 0
1 0 1 1 0
LL
TXD
SCTE
TXCTXC
RXCRXC
RXD
TMTM
RLRL
RTSRTS
DTRDTR
DCD
DSR
CTS
RIRI
RL
RTS
DTR
DCD
DSR
CTS
RI

LTC1343IGW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-232 Interface IC Sftwr-Sel Multiprotocol Tran
Lifecycle:
New from this manufacturer.
Delivery:
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