7
LTC1343
TEST CIRCUITS
Figure 1. RS422 Driver Test Circuit Figure 2. RS422 Driver/Receiver AC Test Circuit
Figure 4. V.10/V.28 Driver Test Circuit Figure 5. V.10/V.28 Receiver Test Circuit
Figure 3. V.35 Driver/Receiver Test Circuit
ODE SELECTIO
W
U
LTC1343 MODE NAME M2 M1 M0 CTRL/CLK D1 D2 D3 D4 R1 R2 R3 R4
V.10, RS423 0 0 0 X V.10 V.10 V.10 V.10 V.10 V.10 V.10 V.10
EIA-530-A Clock and Data 0 0 1 0 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
EIA-530-A Control 0 0 1 1 V.10 V.11 V.10 V.11 V.11 V.10 V.11 V.10
Reserved 0 1 0 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
X.21 0 1 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.35 Clock and Data 1 0 0 0 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28
V.35 Control 1 0 0 1 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
EIA-530, RS449, V.36 1 0 1 X V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.10
V.28, RS232 1 1 0 X V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28
No Cable 1 1 1 X Z Z Z Z Z Z Z Z
A
B
1343 F01
V
OD
V
OC
R
L
50
R
L
50
A
B
A
R
B
1343 F02
R
L
100
C
L
100pF
C
L
100pF
15pF
A
B
D
A
B
1343 F03
R
V
OD
V
CM
50
125
125
50
50
50
15pF
A
D
1343 F04
R
L
C
L
A
D
1343 F04
15pF
R
A
8
LTC1343
SWITCHI G TI E WAVEFOR S
UWW
Figure 6. V.11, V.35 Driver Propagation Delays
Figure 7. V.11, V.35 Receiver Propagation Delays
Figure 8. V.10, V.28 Driver Propagation Delays
Figure 9. V.10, V.28 Receiver Propagation Delays
5V
1.5V 1.5V
50%
10%
90%
t
PLH
t
r
0V
V
O
V
O
–V
O
D
B – A
A
B
t
PHL
t
SKEW
t
SKEW
1343 F06
1/2 V
O
f = 1MHz : t
r
10ns : t
f
10ns
V
DIFF
= V(A) – V(B)
50%
10%
90%
t
f
V
OD2
–V
OD2
0V
1.5V
0V
1.5V
t
PLH
V
OH
V
OL
B – A
R
t
PHL
1343 F07
f = 1MHz : t
r
10ns : t
f
10ns
INPUT
OUTPUT
3V
0V
1.5V
0V
–3V
3V
1.5V
0V
3V
–3V
t
PHL
t
f
V
O
–V
O
D
A
t
PLH
t
r
1343 F08
V
IH
V
IL
1.3V
0.8V
1.7V
2.4V
t
PHL
V
OH
V
OL
A
R
t
PLH
1343 F09
9
LTC1343
APPLICATIONS INFORMATION
WUU
U
software-selectable cable termination chip or by using
existing discrete designs.
A complete DCE-to-DTE interface operating in EIA-530
mode is shown in Figure 10. The first LTC1343 of each port
is used to generate the clock and data signals along with
LL (Local Loop-back) and TM (Test Mode). The second
LTC1343 is used to generate the control signals along with
Figure 10. Complete Multiprotocol Interface in EIA-530 Mode
Overview
The LTC1343 is a 4-driver/4-receiver multiprotocol trans-
ceiver that operates from a single 5V supply. Two LTC1343s
form the core of a complete software-selectable DTE or
DCE interface port that supports the RS232, RS449,
EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable
termination may be implemented using the LTC1344
LTC1343
DCEDTE
LTC1343LTC1344 LTC1344
1343 F10
D1
D4
D4
D3
D2
R1
R4
103
103
103
103
103
R3
LTC1343
D1
D4
D3
D2
R1
R4
R2
R3
LL
TXD
SCTE
TXC
RXC
RXD
TM
LL
TXD
SCTE
TXC
RXC
RXD
TM
SERIAL
CONTROLLER
R3
R2
R1
R4
D3
D2
D1
LTC1343
D4
R3
R2
R1
R4
D3
D2
D1
LL
TXD
SCTE
TXC
RXC
RXD
TM
RL
RTS
DTR
DCD
DSR
CTS
RI
RL
RTS
DTR
DCD
DSR
CTS
RI
RL
RTS
DTR
DCD
DSR
CTS
RI
SERIAL
CONTROLLER
R2

LTC1343IGW#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-232 Interface IC Sftwr-Sel Multiprotocol Tran
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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