ADF4212LBRUZ-RL7 Datasheet ADF4212LBRUZ-RL7, ADF4212LBRUZ, ADF4212LBCPZ | P22-P24

Data Sheet ADF4212L

Rev. E | Page 21 of 28

IF Power-Down

Tabl e 9 shows the power-down bits in the ADF4212L.

IF Fastlock

The IF CP gain bit (P8) of the IF N counter latch register in the

ADF4212L is the fastlock enable bit. Only when P8 is set to 1 is

IF fastlock enabled. When fastlock is enabled, the IF CP current

is set to the maximum value. Also, an extra loop filter damping

resistor to ground is switched in using the FL

pin, thus

compensating for the change in loop characteristics while in

fastlock. Because the IF CP gain bit is contained in the IF N

counter, only one write is needed to both program a new output

frequency and initiate fastlock. To come out of fastlock, the IF

CP gain bit on the IF N counter latch register must be set to 0

(see Table 9).

RF SECTION

Programmable RF Reference (R) Counter

If Control Bits[C2: C1] = 10, the data is transferred from the

input shift register to the 15-bit RF R counter. Table 10 shows

the input shift register data format for the RF R counter and the

divide ratios possible.

RF Phase Detector Polarity

P9 sets the IF phase detector polarity. When the RF VCO

characteristics are positive, P9 should be set to 1. When they are

negative, it should be set to 0 (see Table 10).

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation

(see Table 10).

RF Program Modes

Tabl e 10 shows how to set up the program modes in the

ADF4212L.

RF Charge Pump Currents

RFCP2, RFCP1, and RFCP0 program the current setting for the

RF charge pump. See Table 10.

Programmable RF N Counter

If Control Bits[C2:C1] = 11, the data in the input register is

used to program the RF N (A + B) counter. The N counter

consists of a 6-bit swallow counter (A counter) and a 12-bit

programmable counter (B counter). Table 11 shows the input

divide ratios that are possible.

RF Prescaler Value

P14 and P15 in the RF N counter latch set the RF prescaler

values. See Table 11.

RF Power-Down

Tabl e 11 shows the power-down bits in the ADF4212L.

RF Fastlock

The RF CP gain bit (P17) of the RF N counter latch register in

the ADF4212L is the fastlock enable bit. Only when P17 is set to

1 is IF fastlock enabled. When fastlock is enabled, the RF CP

current is set to the maximum value. Also, an extra loop filter

damping resistor to ground is switched in using the FL

pin,

thus compensating for the change in loop characteristics while

in fastlock. Because the RF CP gain bit is contained in the RF N

counter, only one write is needed to both program a new output

frequency and initiate fastlock. To come out of fastlock, the RF

CP gain bit on the RF N counter latch register must be set to 0.

See

Table 11.

ADF4212L Data Sheet

Rev. E | Page 22 of 28

APPLICATIONS INFORMATION

LOCAL OSCILLATOR FOR GSM HANDSET RECEIVER

Figure 31 shows the ADF4212L being used with a VCO to pro-

duce the required LOs for a GSM base station transmitter or

receiver. The reference input signal is applied to the circuit at

FREF

and, in this case, is terminated in 50 Ω. Typical GSM

systems have a 13 MHz TCXO driving the reference input

without any 50 Ω termination. To have a channel spacing of

200 kHz (the GSM standard), the reference input must be

divided by 65, using the on-chip reference.

The RF output frequency range is 880 MHz to 915 MHz. The

loop filter is designed to give a 20 kHz loop bandwidth. The

filter is set up for a 5 mA charge pump current, and the VCO

sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz. The

filter is again designed to have a bandwidth of 20 kHz, and the

system is programmed to give channel steps of 200 kHz.

SPI-COMPATIBLE SERIAL BUS

LOCK

DETECT

VCO190-902U

REF

DGND

AGND

DGND

AGND

CLK

DATA

MUXOUT

ADF4212L

VCO190-540T

DECOUPLING CAPACITORS (22µF/10pF) ON V

, V

OF THE ADF4212L AND ON V

OF THE VCOs

HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

620pF

1.3nF

13nF

100pF

18Ω

51Ω

1.7kΩ

18Ω

51V

3.3kΩ

OUT

100pF

51Ω

FREF

7kΩ

SET

1nF

8.2nF

620pF

3.3kΩ

5.6kΩ

2 V

02774-036

Figure 31. GSM Handset Receiver Local Oscillator Using the ADF4212L

Data Sheet ADF4212L

Rev. E | Page 23 of 28

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrow band in nature. These applications include the

various wireless standards such as GSM, DSC1800, CDMA, or

WCDMA. In each of these cases, the total tuning range for the

LO is less than 100 MHz. However, there are also wideband

applications where the LO can have up to an octave tuning

range. For example, cable television tuners have a total range

of about 400 MHz. Figure 32 shows an application where the

ADF4212L is used to control and program the Micronetics

M3500-1324. The loop filter was designed for an RF output of

2100 MHz, a loop bandwidth of 40 kHz, a PFD frequency of 1

MHz, I

of 10 mA (2.5 mA synthesizer I

multiplied by the gain

factor of 4), VCO K

of 80 MHz/V (sensitivity of the M3500-1324

at an output of 2100 MHz), and a phase margin of 45 degrees.

In narrow-band applications, there is generally a small variation

in output frequency (generally less than 10%) and a small variation

in VCO sensitivity over the range (typically <10%). However, in

wideband applications, both of these parameters have a much

greater variation, which changes the loop bandwidth. This, in turn,

can affect stability and lock time. By changing the programma-

ble I

, it is possible to obtain compensation for these varying loop

conditions and to ensure that the loop is always operating close

to optimal conditions.

AD820

SPI-COMPATIBLE SERIAL BUS

LOCK

DETECT

DGND

AGND

DGND

AGND

CLK

DATA

OUT

MUXOUT

ADF4212L

100pF

1000pF1000pF

51Ω

18Ω

REF

FREF

SET

3.9nF 27nF

12V

130pF

100pF

470Ω

51Ω

GND

V_TUNE OUT

M3500-1324

2.7kΩ

20kΩ

20V

3kΩ

1kΩ

02774-037

DECOUPLING CAPACITORS ON V

DDx

AND V

OF THE ADF4212L, ON +V

OF THE AD820,

AND ON V

OF THE M3500-1324 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO SIMPLIFY THE SCHEMATIC.

Figure 32. Wideband PLL Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

ADF4212LBRUZ-RL7

Mfr. #:

Buy ADF4212LBRUZ-RL7

Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL Dual Power Freq Synthesizer

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ADF4212LBRUZ-RL7

ADF4212LBRUZ-RL7

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