Data Sheet ADF4212L
Rev. E | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
V
P
1
CP
RF
DGND
RF
FL
O
AGND
RF
RF
IN
V
DD
1
MUXOUT
DGND
IF
REF
IN
20
19
18
17
16
15
14
13
12
11
V
P
2
CP
IF
DGND
IF
R
SET
AGND
IF
IF
IN
CLK
DATA
LE
V
DD
2
ADF4212L
TOP VIEW
(Not to Scale)
2774-003
Figure 3. TSSOP Pin Configuration
CP
RF
DGND
RF
RF
IN
AGND
RF
FL
O
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERM
L PERFORMANCE. THE PAD
SHOULD BE GROUNDED AS WELL.
AGND
IF
IF
IN
DGND
IF
R
SET
LE
REF
IN
DGND
IF
MUXOUT
DATA
CLK
V
DD
V
DD
1
V
P
1
V
P
2
CP
IF
02774-004
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
TOP
VIEW
ADF4212L
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic TSSOP LFCSP Description
CP
RF
3 1
RF Charge Pump Output. When enabled, this provides ±I
CP
to the external RF loop filter, which in turn
drives the external RF VCO.
DGND
RF
4 2 Digital Ground Pin for the RF Digital Circuitry.
RF
IN
5 3 Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.
AGND
RF
6 4 Ground Pin for the RF Analog Circuitry.
FL
O
7 5 Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.
REF
IN
8 6
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ. See Figure 26. This input can be driven from a TTL or CMOS crystal oscillator, or can
be ac-coupled.
DGND
IF
9, 17 7, 15 Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.
MUXOUT 10 8
This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled
reference frequency to be accessed externally.
CLK 11 9
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA 12 10
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high impedance CMOS input.
LE 13 11
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, with the latch selected using the control bits.
R
SET
14 12
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is,
therefore,
SET
MAXCP
R
I
13.5
where R
SET
= 2.7 kΩ and I
CP
MAX
= 5 mA for both the RF and IF charge pumps.
AGND
IF
15 13 Ground Pin for the IF Analog Circuitry.
IF
IN
16 14 Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.
CP
IF
18 16
Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an
external VCO.
V
P
2 19 17
Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where
V
DD
2 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.
