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ADF4212LBRUZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Data Sheet ADF4212L
Rev. E | Page 3 of 28
SPECIFICATIONS
V
DD
1 = V
DD
2 = 2.7 V to 3.3 V; V
P
1, V
P
2 = V
DD
to 5.5 V; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted; dBm referred to 50 Ω.
Table 1.
Parameter
1
B Version B Chips
2
Unit Test Conditions/Comments
RF/IF CHARACTERISTICS
RF Input Frequency (RF
IN
) 0.2/2.4 0.2/2.4 GHz min/max For lower frequencies, ensure that slew rate (SR)
> 140 V/µs
RF Input Sensitivity −10/0 −10/0 dBm min/max V
DD
= 3 V
IF Input Frequency (IF
IN
) 100/1000 100/1000 MHz min/max
IF Input Sensitivity −10/0 −10/0 dBm min/max V
DD
= 3 V
MAXIMUM ALLOWABLE
Prescaler Output Frequency
3
188 188 MHz max
REF
IN
CHARACTERISTICS
See
Figure 26 for input circuit
REF
IN
Input Frequency 10/150 10/150 MHz min/max
REF
IN
Input Sensitivity 500 mV/V
DD
500 mV/V
DD
V p-p min/max AC-coupled; when dc-coupled, 0 V to V
DD
maximum (CMOS compatible)
REF
IN
Input Capacitance 10 10 pF max
REF
IN
Input Current ±100 ±100 μA max
PHASE DETECTOR
Phase Detector Frequency
4
75 75 MHz max
CHARGE PUMP
I
CP
Sink/Source
Programmable, see
Table 10
High Value 5 5 mA typ With R
SET
= 2.7 kΩ
Low Value 625 625 μA typ
Absolute Accuracy 2 2 % typ With R
SET
= 2.7 kΩ
R
SET
Range 1.5/5.6 1.5/5.6 kΩ min/max
I
CP
Three-State Leakage Current 1 1 nA max
Sink and Source Current Matching 6 6 % typ 0.5 V < V
CP
< V
P
− 0.5 V
I
CP
vs. V
CP
2 2 % typ 0.5 V < V
CP
< V
P
− 0.5 V
I
CP
vs. Temperature 2 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 1.4 1.4 V min
V
INL
, Input Low Voltage 0.6 0.6 V max
I
INH
/I
INL
, Input Current ±1 ±1 μA max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 μA
POWER SUPPLIES
V
DD
1 2.7/3.3 2.7/3.3 V min/max
V
DD
2 V
DD
1 V
DD
1 V min/max
V
P
1, V
P
2 V
DD
1/5.5 V
DD
1/5.5 V min/max
I
DD
(RF and IF)
5
7.5/10 7.5/10 mA typ/max
RF Only 5.0/6 5.0/6 mA typ/max
IF Only 2.5/4 2.5/4 mA typ/max
I
P
(I
P
1 + I
P
2) 0.6 0.6 mA typ
Low Power Sleep Mode 1 1 μA typ
1
Operating temperature range is as follows: B version: −40°C to +85°C.
2
The B chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency less
than this value.
4
Guaranteed by design. Sample tested to ensure compliance.
5
T
A
= 25°C. RF = 1 GHz; prescaler = 32/33. IF = 500 MHz; prescaler = 16/17.
ADF4212L Data Sheet
Rev. E | Page 4 of 28
V
DD
1 = V
DD
2 = 2.7 V to 3.3 V; V
P
1, V
P
2 = V
DD
to 5.5 V; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted; dBm referred to 50 V.
Table 2.
Parameter
1
B Version B Chips
2
Unit Test Conditions/Comments
NOISE CHARACTERISTICS
RF Phase Noise Floor
3
−170 −170 dBc/Hz typ 25 kHz PFD frequency
−162 −162 dBc/Hz typ 200 kHz PFD frequency
Phase Noise Performance
4
VCO output
IF: 540 MHz Output
5
−89 −89 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
IF: 900 MHz Output
6
−87 −87 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 900 MHz Output
6
−89 −89 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 1750 MHz Output
7
−84 −84 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 2400 MHz Output
8
−87 −87 dBc/Hz typ 1 kHz Offset and 1 MHz PFD frequency
Spurious Signals
IF: 540 MHz Output
5
−88/−90 −88/−90 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
IF: 900 MHz Output
6
−90/−94 −90/−94 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 900 MHz Output
6
−90/−94 −90/−94 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 1750 MHz Output
7
−80/−82 −80/−82 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 2400 MHz Output
8
−80/−82 −80/−82 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
1
Operating temperature range is as follows: B version: −40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
See Figure 9.
4
The phase noise is measured with the EVAL-ADF4212EB and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer
(f
REFOUT
= 10 MHz at 0 dBm).
5
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; loop B/W = 20 kHz
6
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; loop B/W = 20 kHz
7
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; loop B/W = 20 kHz
8
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; offset frequency = 1 kHz; f
RF
= 2400 MHz; N = 9800; loop B/W = 20 kHz
Data Sheet ADF4212L
Rev. E | Page 5 of 28
TIMING CHARACTERISTICS
V
DD
1 = V
DD
2 = 2.6 V to 3.3 V; V
P
1, V
P
2 = V
DD
to 5.5 V; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; T
A
= T
MIN
to T
MAX
, unless
otherwise noted; dBm referred to 50 Ω.
Table 3.
Parameter
1
Limit at T
MIN
to T
MAX
(B Version) Unit Test Conditions/Comments
t
1
20 ns min LE setup time
t
2
10 ns min Data to clock setup time
t
3
10 ns min Data to clock hold time
t
4
25 ns min Clock high duration
t
5
25
ns min
Clock low duration
t
6
10 ns min Clock to LE setup time
t
7
20 ns min LE pulse width
1
Guaranteed by design but not production tested.
CLK
DATA
LE
LE
DB23 (MSB) DB22 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
02774-002
Figure 2. Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADF4212LBRUZ-RL7

Mfr. #:
Buy ADF4212LBRUZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Dual Power Freq Synthesizer
Lifecycle:
New from this manufacturer.
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