2©2016 Integrated Device Technology, Inc. Revision F, January 14, 2016
853S111B Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1V
CC
Power Positive supply pin.
2 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When
LOW, selects PCLK0/nPCLK0 inputs. LVPECL interface levels. Also
accepts standard LVCMOS input levels.
3 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
4 nPCLK0 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
5V
BB
Output Bias voltage to be connected for single-ended applications.
6 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
7 nPCLK1 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
8V
EE
Power Negative supply pin.
9, 16, 25, 32 V
CCO
Power Output supply pins.
10, 11
nQ9, Q9
Output Differential output pair. LVPECL/ECL interface levels.
12, 13
nQ8, Q8
Output Differential output pair. LVPECL/ECL interface levels.
14, 15
nQ7, Q7
Output Differential output pair. LVPECL/ECL interface levels.
17, 18
nQ6, Q6
Output Differential output pair. LVPECL/ECL interface levels.
19, 20
nQ5, Q5
Output Differential output pair. LVPECL/ECL interface levels.
21, 22
nQ4, Q4
Output Differential output pair. LVPECL/ECL interface levels.
23, 24
nQ3, Q3
Output Differential output pair. LVPECL/ECL interface levels.
26, 27
nQ2, Q2
Output Differential output pair. LVPECL/ECL interface levels.
28, 29
nQ1, Q1
Output Differential output pair. LVPECL/ECL interface levels.
30, 31
nQ0, Q0
Output Differential output pair. LVPECL/ECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLDOWN
Input Pulldown Resistor 75 k
R
VCC/2
RPullup/Pulldown Resistors 50 k
