853S111BYILFT Datasheet 853S111BKILFT, 853S111BYILF, 853S111BYILFT | P7-P9

853S111B Datasheet

Table 4D. ECL DC Characteristics, V

= 0V; V

= -3.8V to -2.375V, T

= -40°C to 85°C

NOTE: Input and output parameters vary 1:1 with V

. V

can vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50 to V

CCO

– 2V.

NOTE 2: Single-ended input operation is limited. V

 3V in LVPECL mode.

NOTE 3: V

should not be less than V

– 0.3V.

NOTE 4: Common mode voltage is defined as V

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

Output High Voltage; NOTE 1 -1.125 -1.025 -0.855 -1.075 -1.005 -0.855 -1.085 -0.97 -0.890 V

Output Low Voltage; NOTE 1 -1.895 -1.755 -1.60 -1.925 -1.78 -1.655 -1.945 -1.765 -1.67 V

Input High Voltage (Single-ended)

-1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V

Input Low Voltage (Single-ended)

-1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V

Output Voltage Reference;

NOTE 2

-1.44 -1.32 -1.44 -1.32 -1.44 -1.32 V

Peak-to-Peak Input Voltage;

NOTE 3

150 800 1300 150 800 1200 150 800 1200 mV

CMR

Input High Voltage Common

Mode Range; NOTE 3, 4

+1.3 0 V

+1.2 0 V

Input

High

Current

PCLK0, PCLK1

nPCLK0, nPCLK1

200 200 200 µA

Input

Low Current

PCLK0, PCLK1 -10 -10 -10 µA

nPCLK0, nPCLK1 -200 -200 -200 µA

853S111B Datasheet

AC Electrical Characteristics

Table 5. AC Characteristics, V

= V

CCO

= -3.8V to -2.375V or , V

= V

CCO

= 2.375V to 3.8V; V

= 0V, T

= -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: All parameters are measured at f  1GHz, unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter

-40°C 25°C 85°C

UnitsMin Typ Max Min Typ Max Min Typ Max

OUT

Output Frequency 2.5 2.5 2.5 GHz

Propagation Delay; NOTE 1 375 475 580 395 495 610 425 530 645 ps

tsk(o) Output Skew; NOTE 2, 4 30 50 30 50 30 50 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 85 150 85 150 85 150 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

0.03 0.13 0.03 0.13 0.03 0.13 ps

/ t

Output Rise/Fall

Time

20% to 80% 751502208015021578150235ps

853S111B Datasheet

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements have

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

Rohde & Schwarz SMA100A Signal Generator 9kHz - 6GHz as

external input to a Hewlett Packard 8133A 3GHz Pulse Generator.

Additive Phase Jitter @ 155.52MHz

12kHz to 20MHz = 0.03ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

853S111BYILFT

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Description:

Clock Buffer 1:10 LVPECL\ECL FANOUT BUFFER

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853S111BYILFT

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