HVLED805 Datasheet HVLED805TR, HVLED805 | P13-P15

HVLED805 Application information

Doc ID 18077 Rev 1 13/29

5.1 Power section and gate driver

The power section guarantees safe avalanche operation within the specified energy rating

as well as high dv/dt capability. The Power MOSFET has a V(BR)DSS of 800V min. and a

typical R

DSon

of 11 Ω.

The gate driver of the power MOSFET is designed to supply a controlled gate current during

both turn-on and turn-off in order to minimize common mode EMI. Under UVLO conditions

an internal pull-down circuit holds the gate low in order to ensure that the power MOSFET

cannot be turned on accidentally.

5.2 High voltage startup generator

Figure 10 shows the internal schematic of the high-voltage start-up generator (HV

generator). It includes an 800 V-rated N-channel MOSFET, whose gate is biased through

the series of a 12 MΩ resistor and a 14 V zener diode, with a controlled, temperature-

compensated current generator connected to its source. The HV generator input is in

common with the DRAIN pin, while its output is the supply pin of the device (Vcc). A mains

“UVLO” circuit (separated from the UVLO of the device that sense Vcc) keeps the HV

generator off if the drain voltage is below V

START

(50 V typical value).

With reference to the timing diagram of Figure 11, when power is applied to the circuit and

the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently

biased to start operating, thus it will draw about 5.5 mA (typical) from the bulk capacitor.

Figure 10. High-voltage start-up generator: internal schematic

Icharge

IHV

CO NT RO L

Mai ns UV LO

Vcc_OK

HV_EN

12 M14 V

S OURCE

DR AIN

Vcc

Application information HVLED805

14/29 Doc ID 18077 Rev 1

Most of this current will charge the bypass capacitor connected between the Vcc pin and

ground and make its voltage rise linearly.

As the Vcc voltage reaches the start-up threshold (13 V typ.) the chip starts operating, the

internal power MOSFET is enabled to switch and the HV generator is cut off by the Vcc_OK

signal asserted high. The IC is powered by the energy stored in the Vcc capacitor.

The chip is able to power itself directly from the rectified mains: when the voltage on the V

pin falls below Vcc

restart

(10.5V typ.), during each MOSFET’s off-time the HV current

generator is turned on and charges the supply capacitor until it reaches the V

CCOn

threshold.

In this way, the self-supply circuit develops a voltage high enough to sustain the operation of

the device. This feature is useful especially during CC regulation, when the flyback voltage

generated by the auxiliary winding alone may not be able to keep Vcc above V

CCrestart

At converter power-down the system will lose regulation as soon as the input voltage falls

below V

Start

. This prevents converter’s restart attempts and ensures monotonic output

voltage decay at system power-down.

Figure 11. Timing diagram: normal power-up and power-down sequences

Vcc

DRAIN

VccON

Vccrestart

Vin

Start

Icharge

5.5 mA

Power-on

Power- off

Normal operation

CV mode

CC mode

Normal operation

Vcc

DRAIN

VccON

Vccrestart

Vin

Start

Icharge

5.5 mA

Power-on

Power- off

Normal operation

CV mode

CC mode

Normal operation

HVLED805 Application information

Doc ID 18077 Rev 1 15/29

5.3 Secondary side demagnetization detection and triggering

block

The demagnetization detection (DMG) and Triggering blocks switch on the power MOSFET

if a negative-going edge falling below 50 mV is applied to the DMG pin. To do so, the

triggering block must be previously armed by a positive-going edge exceeding 100 mV.

This feature is used to detect transformer demagnetization for QR operation, where the

signal for the DMG input is obtained from the transformer’s auxiliary winding used also to

supply the IC.

The triggering block is blanked after MOSFET’s turn-off to prevent any negative-going edge

that follows leakage inductance demagnetization from triggering the DMG circuit

erroneously.

This blanking time is dependent on the voltage on COMP pin: it is T

BLANK

= 30 µs for V

COMP

= 0.9 V, and decreases almost linearly down to T

BLANK

= 6 µs for V

COMP

= 1.3 V

The voltage on the pin is both top and bottom limited by a double clamp, as illustrated in the

internal diagram of the DMG block of Figure 12. The upper clamp is typically located at 3.3

V, while the lower clamp is located at -60mV. The interface between the pin and the auxiliary

winding will be a resistor divider. Its resistance ratio as well as the individual resistance

values will be properly chosen (see “Section 5.5: Constant current operation on page 18”

and “Section 5.6: Voltage feedforward block on page 20”.

Please note that the maximum I

DMG

sunk/sourced current has to not exceed ±2 mA (AMR)

in all the Vin range conditions. No capacitor is allowed between DMG pin and the auxiliary

transformer.

The switching frequency is top-limited below 166 kHz, as the converter’s operating

frequency tends to increase excessively at light load and high input voltage.

A Starter block is also used to start-up the system, that is, to turn on the MOSFET during

converter power-up, when no or a too small signal is available on the DMG pin.

The starter frequency is 2 kHz if COMP pin is below burst mode threshold, i.e. 1 V, while it

becomes 8 kHz if this voltage exceed this value.

Figure 12. DMG block, triggering block

60 mV

DMG

CLAMP

BLAN KI N G

TIME

TURN-ON

LO G IC

ST AR TE R

LE B

Aux

Rfb

Rdmg

To Dr i ver

Fr om C C/ C V Bl o ck

Fr om OCP

DMG

110mV

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

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