PCA9518A_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 3 December 2008 13 of 23
NXP Semiconductors
PCA9518A
Expandable 5-channel I
2
C-bus hub
10. Dynamic characteristics
[1] For operation between published voltage ranges, refer to worst-case parameter in both ranges.
[2] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are
only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific numerical value can only be
given for fixed RC time constants.
[3] The SDA HIGH to LOW propagation delay includes the fall time from V
DD
to 0.5V
DD
of the EXPSDA1 or EXPSCL1 pins and the SDA or
SCL fall time from the quiescent HIGH (usually V
DD
) to below 0.3V
DD
. The SDA and SCL outputs have edge rate control circuits
included which make the fall time almost independent of load capacitance.
[4] The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5V
DD
for the EXPSDA1
or EXPSCL2, the rise time constant for the quiescent LOW to 0.5V
DD
for the EXPSDA1 or EXPSCL1, and the rise time constant from
the quiescent external driven LOW to 0.7V
DD
for the SDA or SCL output. All of these rise times are RC time constants determined by the
external resistance and total capacitance for the various nodes.
Table 6. Dynamic characteristics
V
DD
= 3.0 V to 3.6 V
[1]
; V
SS
=0V; T
amb
=
−
40
°
Cto+85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
PHL
HIGH to LOW propagation delay SDA to SDAn, or
SCL to SCLn;
Figure 7
[2][3]
105 202 389 ns
t
PLH
LOW to HIGH propagation delay SDA to SDAn, or
SCL to SCLn;
Figure 7
[2][4]
110 259 265 ns
t
PHL1
HIGH to LOW propagation delay 1 EXPSDA1 to SDA, or
EXPSCL1 to SCL;
Figure 7
109 193 327 ns
t
PLH1
LOW to HIGH propagation delay 1 EXPSDA1 to SDA, or
EXPSCL1 to SCL;
Figure 7
130 153 179 ns
t
PLH2
LOW to HIGH propagation delay 2 EXPSDA2 to SDA, or
EXPSCL2 to SCL;
Figure 7
160 234 279 ns
t
THL
HIGH to LOW output transition time SDA, SCL; Figure 7 58 110 187 ns
t
TLH
LOW to HIGH output transition time SDA, SCL; Figure 7 - 0.85 RC - ns
t
su
set-up time enable to START condition 300 - - ns
t
h
hold time enable after STOP condition 300 - - ns
