PCA9518APW,512 Datasheet PCA9518APW,518, PCA9518AD,112, PCA9518APW,512 | P7-P9

Product data sheet Rev. 03 — 3 December 2008 7 of 23

NXP Semiconductors

PCA9518A

Expandable 5-channel I

C-bus hub

In order to illustrate what would be seen in a typical application, refer to Figure 6. If the

bus master in Figure 5 were to write to the slave through the PCA9518A, we would see

the waveform shown in Figure 6. This looks like a normal I

C-bus transmission except for

the small foot preceding each clock LOW-to-HIGH transition and proceeding each data

LOW-to-HIGH transition for the master. The foot height is the difference between the LOW

level driven by the master and the higher voltage LOW level driven by the PCA9518A

repeater. Its width corresponds to an effective clock stretching coming from the

PCA9518A that delays the rising edge of the clock. That same magnitude of delay is seen

on the rising edge of the data. The foot on the rising edge of the data is extended through

the 9

clock pulse as the PCA9518A repeats the acknowledge from the slave to the

master. The clock of the slave looks normal except the V

is the ~0.5 V level generated

by the PCA9518A. The SDA at the slave has a particularly interesting shape during the 9

clock cycle where the slave pulls the line below the value driven by the PCA9518A during

Only two of the ﬁve channels on the PCA9518A Device 2 are being used. EN3 and EN4 are connected to V

to disable

channels 3 and 4 and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to V

. SDA0 and SCL0 can be used as a normal I

C-bus

port, but if unused then it must be pulled up to V

since there is no enable pin.

The pull-ups shown on Device 2 channels 3 and 4 are not required if their enable pins (ENn) are permanently held LOW.

Fig 5. Typical application: multiple expandable 5-channel I

C-bus hubs

002aac535

EXPSDA2

EXPSDA1

SCL1

SDA1

EXPSCL1

EXPSCL2

SUBSYSTEM 1

SDA

SCL

400 kHz

5 V

SCL2

SDA2

SUBSYSTEM 2

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

SUBSYSTEM 3

SDA

SCL

100 kHz

5 V

SCL4

SDA4

SUBSYSTEM 4

SDA

SCL

100 kHz

3.3 V

PCA9518A

SCL

SDA

EN2

EN1

EN3

EN4

SCL0

SDA0

DEVICE 1

BUS

MASTER

400 kHz

3.3 V

EN2

EN1

EN3

EN4

SCL4

SDA4

EXPSDA2

EXPSDA1

EXPSCL1

EXPSCL2

PCA9518A

SCL0

SDA0

DEVICE 2

SCL1

SDA1

SUBSYSTEM 5

SDA

SCL

100 kHz

5 V

SCL2

SDA2

SUBSYSTEM 6

SDA

SCL

400 kHz

3.3 V

SCL3

SDA3

3.3 V

or 5 V

3.3 V

or 5 V

disabled;

not connected

Product data sheet Rev. 03 — 3 December 2008 8 of 23

NXP Semiconductors

PCA9518A

Expandable 5-channel I

C-bus hub

the acknowledge and then returns to the PCA9518A level creating a foot before it

completes the LOW-to-HIGH transition. SDA lines other than the one with the master and

the one with the slave have a uniform LOW level driven by the PCA9518A repeater.

The other four waveforms are the expansion bus signals and are included primarily for

timing reference points. All timing on the expansion bus is with respect to 0.5V

EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below

0.3V

. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is ≤0.4 V.

EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below

0.3V

. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is

≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held

below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held

down by the PCA9518A to ~0.5 V until after the delay of the circuit which determines that

it was the last to rise, then it is allowed to rise above the ~0.5 V level driven by the

PCA9518A. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the

EXPSDA1 returns to HIGH after the EXPSDA2 is HIGH and either the bus 0 SDA rise time

is 1 µs or, when the bus 0 SDA reaches 0.7V

, whichever occurs ﬁrst. After both

EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The

same description applies for the EXPSCL1, EXPSCL2, and SCL pins.

Product data sheet Rev. 03 — 3 December 2008 9 of 23

NXP Semiconductors

PCA9518A

Expandable 5-channel I

C-bus hub

It is important to note that any arbitration or clock stretching events on Bus 1 require that

the V

of the devices on Bus 1 be 70 mV below the V

of the PCA9518A (see V

−V

ILc

in the Section 9 “Static characteristics”) to be recognized by the PCA9518A and then

transmitted to Bus 0.

Fig 6. Bus waveforms

Bus 0

of master

SCL of

master

SDA of

master

clock cycle

stretch

of PCA9518A

clock cycle

EXPSDA1

PHL1

EXPSDA2

PHL2

PLH2

, t

PLH1

expansion

bus

EXPSCL1

EXPSCL2

SCL of

slave

SDA of

slave

Bus 1

PHL

PLH

Bus n

with n > 1

of slave V

of PCA9518A

002aac534

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

PCA9518APW,512

Mfr. #:

Buy PCA9518APW,512

Manufacturer:

NXP Semiconductors

Description:

Interface - I/O Expanders EXPNDBL 5-CH I2C HUB

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New from this manufacturer.

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PCA9518APW,512

PCA9518APW,512

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