11
LTC1753
1753fa
Similarly, the MAX comparator forces the output to 0%
duty cycle if V
FB
is more than 3% above the internal
reference. To prevent these two comparators from trig-
gering due to noise, output voltage ripple must be controlled
with sufficient output bypassing to prevent jitter. In addi-
tion, the MIN and MAX comparators’ response times are
deliberately controlled so that they take about one micro-
second to respond. These two comparators help prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
Soft-Start and Current Limit
The LTC1753 includes a soft-start circuit which is used for
initial start-up and during current limit operation. The SS
pin requires an external capacitor to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge the external SS
capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to 100%
duty cycle. The LTC1753 will begin to operate at low duty
cycle as the SS pin rises above about 1.2V (V
COMP
≈ 1.8V).
As SS continues to rise, Q
SS
turns off and the error
amplifier begins to regulate the output. The MIN compara-
tor is disabled when soft-start is active to prevent it from
overriding the soft-start function.
The LTC1753 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the I
FB
pin. CC compares the voltage at I
FB
to the voltage at the I
MAX
pin. As the peak current rises, the
measured voltage across Q1 increases due to the drop
across the R
DS(ON)
of Q1. When the voltage at I
FB
drops
below I
MAX
, indicating that Q1’s drain current has ex-
ceeded the maximum level, CC starts to pull current out of
the external soft-start capacitor, cutting the duty cycle and
controlling the output current level. The CC comparator
pulls current out of the SS pin in proportion to the voltage
difference between I
FB
and I
MAX
. Under minor overload
conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
conventional TTL enable signal. The free-running 300kHz
PWM frequency can be synchronized to a faster external
clock connected to OUTEN. Adjusting the oscillator fre-
quency can add flexibility in the external component
selection. See the Clock Synchronization section.
Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX com-
parators. If the output is ±3% beyond the selected value
for more than 500µs, the PWRGD output will be pulled
low. Once the output has settled within ±3% of the se-
lected value for more than 1ms, PWRGD will return high.
THEORY OF OPERATION
Primary Feedback Loop
The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance
of approximately 108k. This divided down voltage is
subtracted from a reference voltage supplied by the DAC
output. The resulting error voltage is amplified by the error
amplifier and the output is compared to the oscillator ramp
waveform by the PWM comparator. This PWM signal
controls the external MOSFETs through G1 and G2. The
resulting chopped waveform is filtered by L
O
and C
OUT
closing the loop. Loop frequency compensation is achieved
with an external RC + C network at the COMP pin, which is
connected to the output node of the transconductance
amplifier. In low output ripple voltage applications, low
ESR output capacitors are typically used. Under this
condition, a capacitor between the SENSE and V
FB
pins
helps compensate the switching loop. For heavy transient
output loading applications, a small capacitor between the
SENSE and V
FB
pin acts as a feedforward path and helps
reduce the transient recovery time.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifier may not respond quickly enough. MIN compares
the feedback signal V
FB
to a voltage 3% below the internal
reference. If V
FB
is lower than the threshold of this com-
parator, the MIN comparator overrides the ERR
amplifier and forces the loop to 100% duty cycle.
APPLICATIO S I FOR ATIO
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