13
LTC1753
1753fa
mounted next to the external MOSFET which is expected
to run the hottest––often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to V
CC
. Their midpoint
should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Under normal operating conditions, the OUTEN pin should
stay above 1.7V and all circuits will function normally. If
the temperature gets abnormally high, the OUTEN pin
voltage will eventually drop below 1.7V, the LTC1753
disables both FET drivers. If OUTEN decreases below
1.2V, the LTC1753 enters shutdown mode. To activate any
of these three modes, the OUTEN voltage must drop below
the respective threshold for longer than 30µs.
MOSFET Gate Drive
Power for the internal MOSFET drivers is supplied by
PV
CC
. This supply must be above the input supply voltage
by at least one power MOSFET V
GS(ON)
for efficient
opera
tion. For a typical application, PV
CC
should be con-
nected to a 12V power supply.
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V
CC
and PV
CC
power up from a 0V condition, an internal undervoltage
lockout circuit prevents G1 and G2 from going high until
V
CC
reaches about 3.5V. If V
CC
powers up while PV
CC
is at
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC1753 circuits. Logic level MOSFETs should be used
and they should be selected based on on-resistance and
GATE threshold voltage considerations. R
DS(ON)
should
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
GATE threshold voltages for logic level MOSFETs are
lower than standard MOSFETs. A MOSFET whose R
DS(ON)
is rated at V
GS
= 4.5V does not necessarily have a logic
level MOSFET GATE threshold voltage. Using standard
MOSFETs instead of logic level MOSFETs can cause start-
up problems, especially if PV
CC
is derived from a charge
pump scheme. In a typical LTC1753 buck converter circuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
DC Q
V
V
DC Q
V
V
VV
V
OUT
IN
OUT
IN
IN OUT
IN
1
21
()
=
()
=− =
()
Q1
Q2
L
O
V
OUT
1753 F06
C
OUT
V
IN
V
CC
R1
R2
NTC THERMISTOR
MOUNT IN CLOSE
THERMAL PROXIMITY
TO Q1
LTC1753
G1
G2OUTEN
+
Figure 6. OUTEN Pin as a Thermistor Input
Clock Synchronization
The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
the LTC1753 will decrease. Since the loop gain is inversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
when external synchronization is used.
APPLICATIO S I FOR ATIO
WUUU
14
LTC1753
1753fa
The R
DS(ON)
required for a given conduction loss can now
be calculated by rearranging the relation P = I
2
R.
R
P
DC Q I
VP
VI
R
P
DC Q I
VP
VV I
DS ON Q
MAX Q
MAX
IN MAX Q
OUT MAX
DS ON Q
MAX Q
MAX
IN MAX Q
IN OUT MAX
()
()
()
()
()
()
=
()
[]
()
=
()
()()
=
()
[]
()
=
()
()()
1
1
2
1
2
2
2
2
2
2
1
2
P
MAX
should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed with a 5V input and a 2.8V,
11.2A output might allow no more than 4% efficiency loss
at full load for each MOSFET. Assuming roughly 90%
efficiency at this current level, this gives a P
MAX
value of:
[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET
and a required R
DS(ON)
of:
R
VW
VA
R
VW
VV A
DS ON Q
DS ON Q
()
()
=
()( )
()( )
=
=
()( )
()()
=
1
2
2
2
5139
2 8 11 2
0 019
5139
528112
0 025
.
..
.
.
..
.
Note also that while the required R
DS(ON)
values suggest
large MOSFETs, the dissipation numbers are only 1.39W
per device or less––large TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions. Siliconix Si4410DY or International Rectifier IRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
face mount devices with R
DS(ON)
values below 0.03 at 5V
of gate drive that work well in LTC1753 circuits. With
higher output voltages, the R
DS(ON)
of Q1 may need to be
significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher P
MAX
value
Note: Please refer to the manufacturer’s data sheet for testing conditions
and detail information.
Table 4. Recommended MOSFETs for LTC1753 Applications
TYPICAL INPUT
R
DS(ON)
CAPACITANCE
PARTS AT 25°C (m) RATED CURRENT (A) C
ISS
(pF) θ
JC
(°C/W) T
JMAX
(°C)
Siliconix SUD50N03-10 19 15 at 25°C 3200 1.8 175
D-PAK 10 at 100°C
Siliconix Si4410DY 20 10 at 25°C 2700 150
SO-8 8 at 75°C
ON Semiconductor MTD20N03HDL 35 20 at 25°C 880 1.67 150
D PAK 16 at 100°C
Fairchild FDS6670A 8 13 at 25°C 3200 25 150
SO-8
Fairchild FDS6680 10 11.5 at 25°C 2070 25 150
SO-8
ON Semiconductor MTB75N03HDL 7.5 75 at 25°C 4025 1.0 150
DD PAK 59 at 100°C
IR IRL3103S 14 56 at 25°C 1600 1.8 175
DD PAK 40 at 100°C
IR IRLZ44 28 50 at 25°C 3300 1.0 175
TO-220 36 at 100°C
Fuji 2SK1388 37 35 at 25°C 1750 2.08 150
TO-220
APPLICATIO S I FOR ATIO
WUUU
15
LTC1753
1753fa
in the R
DS(ON)
calculations will generally decrease MOSFET
cost and circuit efficiency while increasing MOSFET heat
sink requirements.
Inductor Selection
The inductor is often the largest component in the LTC1753
design and should be chosen carefully. Inductor value and
type should be chosen based on output slew rate require-
ments, output ripple requirements and expected peak
current. Inductor value is primarily controlled by the
required current slew rate. The maximum rate of rise of
current in the inductor is set by its value, the input-to-
output voltage differential and the maximum duty cycle of
the LTC1753. In a typical 5V input, 2.8V output applica-
tion, the maximum current slew rate will be:
DC
VV
LL
A
s
MAX
IN OUT
()
=
183.
µ
where L is the inductor value in µH. With proper frequency
compensation, the combination of the inductor and output
capacitor will determine the transient recovery time. In
general, a smaller value inductor will improve transient
response at the expense of increased output ripple voltage
and inductor core saturation rating. A 2µH inductor would
have a 0.9A/µs rise time in this application, resulting in a
5.5µs delay in responding to a 5A load current step. During
this 5.5µs, the difference between the inductor current and
the output current must be made up by the output capaci-
tor, causing a temporary voltage droop at the output. To
minimize this effect, the inductor value should usually be
in the 1µH to 5µH range for most typical 5V input LTC1753
circuits. To optimize performance, different combinations
of input and output voltages and expected loads may
require different inductor values.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
I
VV V
fLV
RIPPLE
IN OUT OUT
OSC O IN
=
()()
()()()
f
OSC
= LTC1753 oscillator frequency = 300kHz
L
O
= Inductor value
Solving this equation with our typical 5V to 2.8V applica-
tion with a 2µH inductor, we get:
22 056
300 2
2
..
()( )
()()
=
kHz H
A
µ
P-P
Peak inductor current at 11.2A load:
11 2
2
2
12 2..A
A
A+=
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductors with gradual saturation characteristics are often
the best choice.
Input and Output Capacitors
A typical LTC1753 design puts significant demands on
both the input and the output capacitors. During constant
load operation, a buck converter like the LTC1753 draws
square waves of current from the input supply at the
switching frequency. The peak current value is equal to the
output load current plus 1/2 peak-to-peak ripple current,
and the minimum value is zero. Most of this current is
supplied by the input bypass capacitor. The resulting RMS
current flow in the input capacitor will heat it up, causing
premature capacitor failure in extreme cases. Maximum
RMS current occurs with 50% PWM duty cycle, giving an
RMS current value equal to I
OUT
/2. A low ESR input
capacitor with an adequate ripple current rating must be
used to ensure reliable operation.
APPLICATIO S I FOR ATIO
WUUU

LTC1753CSW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5-B Progmable Sync Sw Reg Cntr for Penti
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union