TR1001 Datasheet TR1001 | P4-P6

TR1001 (R) 10/16/14 Page 4 of 12

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ASH Receiver Block Diagram & Timing Cycle

Antenna

Pulse

Generator

SAW

Delay Line

SAW Filter RFA1 RFA2

Data

Out

Detector &

Low-Pass

Filter

RF Data Pulse

P1 P2

RFA1 Out

RF Input

Delay Line

Out

PW2

PW1

PRI

PRC

Figure 1

ASH Transceiver Theory of Operation

Introduction

Murata’s amplifier-sequenced hybrid (ASH) transceiver is

specifically designed for short-range wireless data communication

applications. The transceiver provides robust operation, very small

size, low power consumption and low implementation cost. All

critical RF functions are contained in the hybrid, simplifying and

speeding design-in. The ASH transceiver can be readily

configured to support a wide range of data rates and protocol

requirements. The transceiver features excellent suppression of

transmitter harmonics and virtually no RF emissions when

receiving, making it easy to certify to short- range (unlicensed)

radio regulations.

Amplifier-Sequenced Receiver Operation

The ASH transceiver’s unique feature set is made possible by its

system architecture. The heart of the transceiver is the amplifier-

sequenced receiver section, which provides more than 100 dB of

stable RF and detector gain without any special shielding or

decoupling provisions. Stability is achieved by distributing the total

RF gain over time. This is in contrast to a superheterodyne

receiver, which achieves stability by distributing total RF gain over

multiple frequencies.

Figure 1 shows the basic block diagram and timing cycle for an

amplifier-sequenced receiver. Note that the bias to RF amplifiers

RFA1 and RFA2 are independently controlled by a pulse

generator, and that the two amplifiers are coupled by a surface

acoustic wave (SAW) delay line, which has a typical delay of 0.5

µs.

An incoming RF signal is first filtered by a narrow-band SAW filter,

and is then applied to RFA1. The pulse generator turns RFA1 ON

for 0.5 µs. The amplified signal from RFA1 emerges from the SAW

delay line at the input to RFA2. RFA1 is now switched OFF and

RFA2 is switched ON for 0.55 µs, amplifying the RF signal further.

The ON time for RFA2 is usually set at 1.1 times the ON time for

RFA1, as the filtering effect of the SAW delay line stretches the

signal pulse from RFA1 somewhat. As shown in the timing

diagram, RFA1 and RFA2 are never on at the same time, assuring

excellent receiver stability. Note that the narrow-band SAW filter

eliminates sampling sideband responses outside of the receiver

passband, and the SAW filter and delay line act together to provide

very high receiver ultimate rejection.

Amplifier-sequenced receiver operation has several interesting

characteristics that can be exploited in system design. The RF

amplifiers in an amplifier-sequenced receiver can be turned on and

off almost instantly, allowing for very quick power-down (sleep)

and wake-up times. Also, both RF amplifiers can be off between

ON sequences to trade-off receiver noise figure for lower average

current consumption. The effect on noise figure can be modeled as

if RFA1 is on continuously, with an attenuator placed in front of it

with a loss equivalent to 10*log

(RFA1 duty factor), where the

duty factor is the average amount of time RFA1 is ON (up to 50%).

TR1001 (R) 10/16/14 Page 5 of 12

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Figure 2

Since an amplifier-sequenced receiver is inherently a sampling

receiver, the overall cycle time between the start of one RFA1 ON

sequence and the start of the next RFA1 ON sequence should be

set to sample the narrowest RF data pulse at least 10 times.

Otherwise, significant edge jitter will be added to the detected data

pulse.

ASH Transceiver Block Diagram

Figure 2 is the general block diagram of the ASH transceiver.

Please refer to Figure 2 for the following discussions.

Antenna Port

The only external RF components needed for the transceiver are

the antenna and its matching components. Antennas presenting

an impedance in the range of 35 to 72 ohms resistive can be

satisfactorily matched to the RFIO pin with a series matching coil

and a shunt matching/ESD protection coil. Other antenna

impedances can be matched using two or three components. For

some impedances, two inductors and a capacitor will be required.

A DC path from RFIO to ground is required for ESD protection.

Receiver Chain

The output of the SAW filter drives amplifier RFA1. This amplifier

includes provisions for detecting the onset of saturation (AGC Set),

and for switching between 35 dB of gain and 5 dB of gain (Gain

Select). AGC Set is an input to the AGC Control function, and Gain

Select is the AGC Control function output. ON/OFF control to

RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp

Bias function. The output of RFA1 drives the SAW delay line, which

has a nominal delay of 0.5 µs.

The second amplifier, RFA2, provides 51 dB of gain below

saturation. The output of RFA2 drives a full-wave detector with

19 dB of threshold gain. The onset of saturation in each section of

RFA2 is detected and summed to provide a logarithmic response.

This is added to the output of the full-wave detector to produce an

overall detector response that is square law for low signal levels,

and transitions into a log response for high signal levels. This

combination provides excellent threshold sensitivity and more than

70 dB of detector dynamic range. In combination with the 30 dB of

AGC range in RFA1, more than 100 dB of receiver dynamic range

is achieved.

The detector output drives a gyrator filter. The filter provides a

three-pole, 0.05 degree equiripple low-pass response with

excellent group delay flatness and minimal pulse ringing. The 3 dB

bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an

external resistor.

The filter is followed by a base-band amplifier which boosts the

detected signal to the BBOUT pin. When the receiver RF amplifiers

are operating at a 50%-50% duty cycle, the BBOUT signal

changes about 10 mV/dB, with a peak-to-peak signal level of up to

685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak

signal level are proportionately less. The detected signal is riding

on a 1.1 Vdc level that varies somewhat with supply voltage,

temperature, etc. BBOUT is coupled to the CMPIN pin or to an

external data recovery process (DSP, etc.) by a series capacitor.

The correct value of the series capacitor depends on data rate,

data run length, and other factors as discussed in the ASH

Transceiver Designer’s Guide.

When an external data recovery process is used with AGC,

BBOUT must be coupled to the external data recovery process

and CMPIN by separate series coupling capacitors. The AGC

reset function is driven by the signal applied to CMPIN.

ASH Transceiver Block Diagram

RFA1 RFA2

TXA1TXA2

SAW

Delay Line

SAW

CR Filter

Log

Antenna

RFIO

Tuning/ESD

Detector

Low-Pass

Filter

AGC

Control

Peak

Detector

Pulse Generator

& RF Amp Bias

LPFADJ

PRATE

PWIDTH

RXDATA

TXMOD

TRL1

TRL0

AGCCAP

REF

THLD2THLD1

Modulation

& Bias Control

Power Down

Control

Gain Select

AGC Set

AGC Reset

Threshold

Control

BBOUT

DS2

DS1

AND

dB Below

Peak Thld

Ref Thld

PKDET

Ref

AGC

BBO

PKD

LPF

AGC

TH2

TH1

TXM

11 12

VCC1: Pin 2

VCC2: Pin 16

GND1: Pin 1

GND2: Pin 10

GND3: Pin 19

RREF: Pin 11

CMPIN: Pin 6

Tuning

TR1001 (R) 10/16/14 Page 6 of 12

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When the transceiver is placed in the power-down (sleep) or in a

transmit mode, the output impedance of BBOUT becomes very

high. This feature helps preserve the charge on the coupling

capacitor to minimize data slicer stabilization time when the

transceiver switches back to the receive mode.

Data Slicers

The CMPIN pin drives two data slicers, which convert the analog

signal from BBOUT back into a digital stream. The best data slicer

choice depends on the system operating parameters. Data slicer

DS1 is a capacitively-coupled comparator with provisions for an

adjustable threshold. DS1 provides the best performance at low

signal-to-noise conditions. The threshold, or squelch, offsets the

comparator’s slicing level from 0 to 90 mV, and is set with a resistor

between the RREF and THLD1 pins. This threshold allows a trade-

off between receiver sensitivity and output noise density in the no-

signal condition. For best sensitivity, the threshold is set to 0. In

this case, noise is output continuously when no signal is present.

This, in turn, requires the circuit being driven by the RXDATA pin

to be able to process noise (and signals) continuously.

This can be a problem if RXDATA is driving a circuit that must

“sleep” when data is not present to conserve power, or when it its

necessary to minimize false interrupts to a multitasking processor.

In this case, noise can be greatly reduced by increasing the

threshold level, but at the expense of sensitivity. The best 3 dB

bandwidth for the low-pass filter is also affected by the threshold

level setting of DS1. The bandwidth must be increased as the

threshold is increased to minimize data pulse-width variations with

signal amplitude.

Data slicer DS2 can overcome this compromise once the signal

level is high enough to enable its operation. DS2 is a “dB-below-

peak” slicer. The peak detector charges rapidly to the peak value

of each data pulse, and decays slowly in between data pulses

(1:1000 ratio). The slicer trip point can be set from 0 to 120 mV

below this peak value with a resistor between RREF and THLD2.

A threshold of 60 mV is the most common setting, which equates

to “6 dB below peak” when RFA1 and RFA2 are running a 50%-

50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the

signal amplitude to data pulse-width variation, allowing a lower 3

dB filter bandwidth to be used for improved sensitivity.

DS2 is best for ASK modulation where the transmitted waveform

has been shaped to minimize signal bandwidth. However, DS2 is

subject to being temporarily “blinded” by strong noise pulses,

which can cause burst data errors. Note that DS1 is active when

DS2 is used, as RXDATA is the logical AND of the DS1 and DS2

outputs. DS2 can be disabled by leaving THLD2 disconnected. A

non-zero DS1 threshold is required for proper AGC operation.

AGC Control

The output of the Peak Detector also provides an AGC Reset

signal to the AGC Control function through the AGC comparator.

The purpose of the AGC function is to extend the dynamic range

of the receiver, so that the receiver can operate close to its

transmitter when running ASK and/or high data rate modulation.

The onset of saturation in the output stage of RFA1 is detected and

generates the AGC Set signal to the AGC Control function. The

AGC Control function then selects the 5 dB gain mode for RFA1.

The AGC Comparator will send a reset signal when the Peak

Detector output (multiplied by 0.8) falls below the threshold voltage

for DS1.

A capacitor at the AGCCAP pin avoids AGC “chattering” during the

time it takes for the signal to propagate through the low-pass filter

and charge the peak detector. The AGC capacitor also allows the

hold-in time to be set longer than the peak detector decay time to

avoid AGC chattering during runs of “0” bits in the received data

stream. Note that AGC operation requires the peak detector to be

functioning, even if DS2 is not being used. AGC operation can be

defeated by connecting the AGCCAP pin to Vcc. The AGC can be

latched on once engaged by connecting a 150 kilohm resistor

between the AGCCAP pin and ground in lieu of a capacitor.

Receiver Pulse Generator and RF Amplifier Bias

The receiver amplifier-sequence operation is controlled by the

Pulse Generator & RF Amplifier Bias module, which in turn is

controlled by the PRATE and PWIDTH input pins, and the Power

Down (sleep) Control Signal from the Bias Control function.

In the low data rate mode, the interval between the falling edge of

one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse

PRI

is set by a resistor between the PRATE pin and ground. The

interval can be adjusted between 0.1 and 5 µs. In the high data rate

mode (selected at the PWIDTH pin) the receiver RF amplifiers

operate at a nominal 50%-50% duty cycle. In this case, the start-

to-start period t

PRC

for ON pulses to RFA1 are controlled by the

PRATE resistor over a range of 0.1 to 1.1 µs.

In the low data rate mode, the PWIDTH pin sets the width of the

ON pulse t

PW1

to RFA1 with a resistor to ground (the ON pulse

width t

PW2

to RFA2 is set at 1.1 times the pulse width to RFA1 in

the low data rate mode). The ON pulse width t

PW1

can be adjusted

between 0.55 and 1 µs. However, when the PWIDTH pin is

connected to Vcc through a 1 M resistor, the RF amplifiers operate

at a nominal 50%-50% duty cycle, facilitating high data rate

operation. In this case, the RF amplifiers are controlled by the

PRATE resistor as described above.

Both receiver RF amplifiers are turned off by the Power Down

Control Signal, which is invoked in the sleep and transmit modes.

Transmitter Chain

The transmitter chain consists of a SAW delay line oscillator

followed by a modulated buffer amplifier. The SAW filter

suppresses transmitter harmonics to the antenna. Note that the

same SAW devices used in the amplifier-sequenced receiver are

reused in the transmit modes.

Transmitter operation supports two modulation formats, on-off

keyed (OOK) modulation, and amplitude-shift keyed (ASK)

modulation. When OOK modulation is chosen, the transmitter

output turns completely off between “1” data pulses. When ASK

modulation is chosen, a “1” pulse is represented by a higher

transmitted power level, and a “0” is represented by a lower

transmitted power level. OOK modulation provides compatibility

with first-generation ASH technology, and provides for power

conservation. ASK modulation must be used for high data rates

(data pulses less than 30 µs). ASK modulation also reduces the

effects of some types of interference and allows the transmitted

pulses to be shaped to control modulation bandwidth.

The modulation format is chosen by the state of the CNTRL0 and

the CNTRL1 mode control pins, as discussed below. When either

modulation format is chosen, the receiver RF amplifiers are turned

off. In the OOK mode, the delay line oscillator amplifier TXA1 and

buffer amplifier TXA2 are turned off when the voltage to the

TXMOD input falls below 220 mV. In the OOK mode, the data rate

is limited by the turn-on and turn-off times of the delay line

oscillator, which are 12 and 6 µs respectively. In the ASK mode

TXA1 is biased ON continuously, and the output of TXA2 is

modulated by the TXMOD input current. Minimum output power

occurs in the ASK mode when the modulation driver sinks about

10 µA of current from the TXMOD pin.

The transmitter RF output power is proportional to the input current

to the TXMOD pin. A series resistor is used to adjust the peak

transmitter output power. 1.5 dBm of output power requires about

450 µA of input current.

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TR1001

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RF Receiver 2G ASH Transceiver 868.35MHz 115.2kbps

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