©2010-2014 by Murata Electronics N.A., Inc.
TR1001 (R) 10/16/14 Page 7 of 12
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Transceiver Mode Control
The four transceiver operating modes – receive, transmit ASK,
transmit OOK, and power-down (sleep), are controlled by the
Modulation & Bias Control function, and are selected with the
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
both high place the unit in the receive mode. Setting CNTRL1 high
and CNTRL0 low place the unit in the ASK transmit mode. Setting
CNTRL1 low and CNTRL0 high place the unit in the OOK transmit
mode. Setting CNTRL1 and CNTRL0 both low place the unit in the
power-down (sleep) mode. Note that the resistor driving TXMOD
must be low in the receive and power-down modes. The PWIDTH
resistor must also be low in the power down mode to minimize
current. CNTRL1 and CNTRL0 are CMOS compatible inputs.
These inputs must be held at a logic level; they cannot be left
unconnected.
Transceiver Event Timing
Transceiver event timing is summarized in Table 1. Please refer to
this table for the following discussions.
Turn-On Timing
The maximum time t
PR
required for the receive function to become
operational at turn on is influenced by two factors. All receiver
circuitry will be operational 5 ms after the supply voltage reaches
2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC
stabilized in 3 time constants
(3*t
BBC
). The total turn-on time to stable receiver operation for a 10
ms power supply rise time is:
t
PR
= 15 ms + 3*t
BBC
The maximum time required for either the OOK or ASK transmitter
mode to become operational is 5 ms after the supply voltage
reaches 2.2 Vdc.
Receive-to-Transmit Timing
After turn on, the maximum time required to switch from receive to
either transmit mode is 12 µs. Most of this time is due to the start-
up of the transmitter oscillator.
Transmit-to-Receive Timing
The maximum time required to switch from the OOK or ASK
transmit mode to the receive mode is 3*t
BBC
, where t
BBC
is the
BBOUT- CMPIN coupling-capacitor time constant. When the
operating temperature is limited to 60
o
C, the time required to
switch from transmit to receive is dramatically less for short
transmissions, as less charge leaks away from the
BBOUT-CMPIN coupling capacitor.
Sleep and Wake-Up Timing
The maximum transition time from the receive mode to the power-
down (sleep) mode t
RS
is 10 µs after CNTRL1 and CNTRL0 are
both low (1 µs fall time).
The maximum transition time from either transmit mode to the
sleep mode (t
TOS
and t
TAS
) is 10 µs after CNTRL1 and CNTRL0
are both low (1 µs fall time).
The maximum transition time t
SR
from the sleep mode to the
receive mode is 3*t
BBC
, where t
BBC
is the BBOUT-CMPIN
coupling-capacitor time constant. When the operating temperature
is limited to 60
o
C, the time required to switch from sleep to receive
is dramatically less for short sleep times, as less charge leaks
away from the BBOUT- CMPIN coupling capacitor.
The maximum time required to switch from the sleep mode to
either transmit mode (t
STO
and t
STA
) is 16 µs. Most of this time is
due to the start-up of the transmitter oscillator.
AGC Timing
The maximum AGC engage time t
AGC
is 5 µs after the reception of
a -30 dBm RF signal with a 1 µs envelope rise time.
The minimum AGC hold-in time is set by the value of the capacitor
at the AGCCAP pin. The hold-in time t
AGH
= C
AGC
/19.1, where
t
AGH
is in µs and C
AGC
is in pF.
Peak Detector Timing
The Peak Detector attack time constant is set by the value of the
capacitor at the PKDET pin. The attack time t
PKA
= C
PKD
/4167,
where t
PKA
is in µs and C
PKD
is in pF. The Peak Detector decay
time constant t
PKD
= 1000*t
PKA
.
Pulse Generator Timing
In the low data rate mode, the interval t
PRI
between the falling edge
of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor R
PR
between the PRATE pin and ground. The interval can be adjusted
between 0.1 and 5 µs with a resistor in the range of 51 K to 2000
K. The value of the R
PR
is given by:
R
PR
= 404* t
PRI
+ 10.5, where t
PRI
is in µs, and R
PR
is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the
receiver RF amplifiers operate at a nominal 50%-50% duty cycle.
In this case, the period t
PRC
from the start of an ON pulse to the
first RF amplifier to the start of the next ON pulse to the first RF
amplifier is controlled by the PRATE resistor over a range of 0.1 to
1.1 µs using a resistor of 11 K to 220 K. In this case R
PR
is given
by:
R
PR
= 198* t
PRC
- 8.51, where t
PRC
is in µs and R
PR
is in kilohms
In the low data rate mode, the PWIDTH pin sets the width of the
ON pulse to the first RF amplifier t
PW1
with a resistor R
PW
to
ground (the ON pulse width to the second RF amplifier t
PW2
is set
at 1.1 times the pulse width to the first RF amplifier in the low data
rate mode). The ON pulse width t
PW1
can be adjusted between
0.55 and 1 µs with a resistor value in the range of 200 K to 390 K.
The value of R
PW
is given by:
R
PW
= 404* t
PW1
- 18.6, where t
PW1
is in µs and R
PW
is in kilohms
However, when the PWIDTH pin is connected to Vcc through a 1
M resistor, the RF amplifiers operate at a nominal 50%-50% duty
cycle, facilitating high data rate operation. In this case, the RF
amplifiers are controlled by the PRATE resistor as described
above.
LPF Group Delay
The low-pass filter group delay is a function of the filter 3 dB
bandwidth, which is set by a resistor R
LPF
to ground at the LPFADJ
pin. The minimum 3 dB bandwidth f
LPF
= 1445/R
LPF
, where f
LPF
is
in kHz, and R
LPF
is in kilohms.
The maximum group delay t
FGD
= 1750/f
LPF
= 1.21*R
LPF
, where
t
FGD
is in µs, f
LPF
in kHz, and R
LPF
in kilohms.
©2010-2014 by Murata Electronics N.A., Inc.
TR1001 (R) 10/16/14 Page 8 of 12
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Transceiver Event Timing, 3.0 Vdc, -40 to +85 °C
Event Symbol Time Min/Max Test Conditions Notes
Turn On to Receive
t
PR
3*t
BBC
+ 15 ms
max 10 ms supply voltage rise time time until receiver operational
Turn On to TXOOK
t
PTO
15 ms max 10 ms supply voltage rise time time until TXMOD can modulate transmitter
Turn On to TXASK
t
PTA
15 ms max 10 ms supply voltage rise time time until TXMOD can modulate transmitter
RX to TXOOK
t
RTO
12 µs max 1 µs CNTRL1 fall time TXMOD low 1 µs before CNTRL1 falls
RX to TXASK
t
RTA
12 µs max 1 µs CNTRL0 fall time TXMOD low 1 µs before CNTRL0 falls
TXOOK to RX
t
TOR
3*t
BBC
max 1 µs CNTRL1 rise time time until receiver operational
TXASK to RX
t
TAR
3*t
BBC
max 1 µs CNTRL0 rise time time until receiver operational
Sleep to RX
t
SR
3*t
BBC
max 1 µs CNTRL0/CNTROL 1 rise times time until receiver operational
Sleep to TXOOK
t
STO
16 µs max 1 µs CNTRL0 rise time time until TXMOD can modulate transmitter
Sleep to TXASK
t
STA
16 µs max 1 µs CNTRL1 rise time time until TXMOD can modulate transmitter
RX to Sleep
t
RS
10 µs max 1 µs CNTRL0/CNTROL 1 fall times time until transceiver is in power-downmode
TXOOK to Sleep
t
TOS
10 µs max 1 µs CNTRL0 fall time time until transceiver is in power-downmode
TXASK to Sleep
t
TAS
10 µs max 1 µs CNTRL1 fall time time until transceiver is in power-downmode
AGC Engage
t
AGC
5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain
AGE Hold-In
t
AGH
C
AGC
/19.1
min
C
AGC
in pF, t
AGH
in µs user selected; longer than t
PKD
PKDET Attack Time Constant
t
PKA
C
PKD
/4167
min
C
PKD
in pF, t
PKA
in µs
user selected
PKDET Decay Time Constant
t
PKD
1000*t
PKA
min
t
PKD
and t
PKA
in µs
slaved to attack time
PRATE Interval
t
PRI
0.1 to 5 µs range low data rate mode user selected mode
PWIDTH RFA1
t
PW1
0.55 to 1 µs range low data rate mode user selected mode
PWIDTH RFA2
t
PW2
1.1*t
PW1
range low data rate mode user selected mode
PRATE Cycle
t
PRC
0.1 to 1.1 µs range high data rate mode user selected mode
PWIDTH High (RFA1 & RFA2)
t
PWH
0.05 to 0.55 µs range high data rate mode user selected mode
LPF Group Delay
t
FGD
1750/f
LPF
max
t
FGD
in µs, f
LPF
in kHz
user selected
LPF 3 dB Bandwidth
f
LPF
1445/R
LPF
min
f
LPF
in kHz, R
LPF
in kilohms
user selected
BBOUT-CMPIN Time Constant
t
BBC
0.064*C
BBO
min
t
BBC
in µs, C
BBO
in pF
user selected
Table 1
©2010-2014 by Murata Electronics N.A., Inc.
TR1001 (R) 10/16/14 Page 9 of 12
www.murata.com
Pin Descriptions
Pin Name Description
1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.
2 VCC1
VCC1 is the positive supply voltage pin for the transmitter output amplifier and the receiver base-band circuitry. VCC1 is
usually connected to the positive supply through a ferrite RF decoupling bead, which is bypassed by an RF capacitor on the
supply side. See the ASH Transceiver Designer’s Guide for additional information.
3 AGCCAP
This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will hold-
in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time t
AGH
, the capacitor value C
AGC
is:
C
AGC
= 19.1* t
AGH
,where t
AGH
is in µs and C
AGC
is in pF
A ±10% ceramic capacitor should be used at this pin. The value of C
AGC
given above provides a hold-in time between t
AGH
and 2.65* t
AGH
, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride
through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the
peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will
be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when
using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to Vcc.
Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC can be
latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation
depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down
(sleep) mode and in the transmit modes.
4PKDET
This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and
decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the
base-band time constant. For a given base-band capacitor C
BBO
, the capacitor value C
PKD
is:
C
PKD
= 0.33* C
BBO
, where C
BBO
and C
PKD
are in pF
A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t
PKA
and 1.5* t
PKA
with variations
in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K
load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC hold-in time
can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates
and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin and
the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number of external compo-
nents needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode and in the transmit
modes.
5 BBOUT
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C
BBO
for internal
data slicer operation. The time constant t
BBC
for this connection is:
t
BBC
= 0.064*C
BBO
, where t
BBC
is in µs and C
BBO
is in pF
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t
BBC
and
1.8*t
BBC
with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend
on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common crite-
ria is to set the time constant for no more than a 20% voltage droop during SP
MAX
. For this case:
C
BBO
= 70*SP
MAX
, where SP
MAX
is the maximum signal pulse width in µs and C
BBO
is in pF
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped-
ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak
signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt-
age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in
parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must
be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function
is driven by the signal applied to CMPIN. When the transceiver is in power-down (sleep) or in a transmit mode, the output
impedance of this pin becomes very high, preserving the charge on the coupling capacitor.
6CMPIN
This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of
this pin is 70 K to 100 K.
7RXDATA
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this
pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or transmit modes, this pin
becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state
when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no
greater than Vcc + 200 mV.

TR1001

Mfr. #:
Manufacturer:
Murata Electronics
Description:
RF Receiver 2G ASH Transceiver 868.35MHz 115.2kbps
Lifecycle:
New from this manufacturer.
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