LTC2489
10
2489fb
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CONVERTER OPERATION
Converter Operation Cycle
The LTC2489 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I
2
C interface. Its
operation is made up of four states (see Figure 1). The
converter operating cycle begins with the conversion,
followed by the sleep state and ends with the data input/
output cycle .
applicaTions inForMaTion
Figure 1. State Transition Table
CONVERSION
SLEEP
2489 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24 BITS
DATA OUTPUT/INPUT
POWER-ON RESET
DEFAULT INPUT CHANNEL:
IN
+
= CH0, IN
= CH1
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 24
bits read out of the device).
Ease of Use
The L
TC2489 data output has no latency
, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion,
immediately following a newly selected input is valid and
accurate to the full specifications of the device.
The LTC2489 automatically performs offset and full-scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent
to the user and has no effect on the operation cycle de
-
scribed above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
Easy Drive Input Current Cancellation
The L
TC2489 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietar
y front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sen
-
sors to directly interface to the LTC2489 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input im
-
pedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
Input Current Cancellation section). This unique architec
-
ture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and V
CC
. Moreover, the
cancellation does not interfere with the transparent offset
Initially, at power-up, the LTC2489 performs a conver-
sion. Once the conversion is complete, the device enters
the sleep state. In the sleep state, power consumption is
reduced by two orders of magnitude. The part remains
in the sleep state as
long it is not addressed for a read/
write operation. The conversion result is held indefinitely
in a static shift register while the part is in the sleep state.
The device will not acknowledge an external request dur
-
ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2489 is addressed for a read operation, the device
LTC2489
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and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2489 automatically enters an internal reset state
when the power supply voltage, V
CC
, drops below ap-
proximately 2.0V. This feature guarantees the integrity of
the conversion result and input channel selection.
When V
CC
rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channels IN
+
= CH0 and
IN
= CH1. The first conversion following a POR cycle
is accurate within the specification of the device if the
power supply voltage is restored to (2.7V to 5.5V) before
the end of the POR interval. A new input channel can be
programmed into the device during this first data input/
output cycle.
Reference Voltage Range
This converter accepts a truly differential, external refer
-
ence voltage. The absolute/common mode voltage range
for the REF
+
and REF
pins covers the entire operating
range of the device (GND to V
CC
). For correct converter
operation, V
REF
must be positive (REF
+
> REF
).
The LTC2489 differential reference input range is 0.1V to
V
CC
. For the simplest operation, REF
+
can be shorted to
V
CC
and REF
can be shorted to GND. The converter out-
put noise is determined by the thermal noise of the front
end circuits. Since the transition noise is well below 1LSB
(0.02LSB), a decrease in reference voltage will proportion
-
ally improve the converter resolution and improve INL.
Input Voltage Range
The
LTC2489 input measurement range is –0.5V
REF
to
+0.5V
REF
in both differential and single-ended configura-
tions as shown in Figure 27. Highest linearity is achieved with
Fully Differential drive and a constant common-mode voltage
(Figure 27b). Other drive schemes may incur an INL error
of approximately 50ppm. This error can be calibrated out
using a three point calibration and a second-order curve fit.
The analog inputs are truly differential with an absolute,
common mode range for the CH0-CH3 and COM input
pins extending from GND – 0.3V to V
CC
+ 0.3V. Within
these limits, the LTC2489 converts the bipolar differen-
tial input signal V
IN
= IN
+
– IN
(where IN
+
and IN
are
the selected input channels), from –FS = –0.5 V
REF
to +FS = 0.5 V
REF
where V
REF
= REF
+
- REF
. Outside this
range, the converter indicates the overrange or the under-
range condition using distinct output codes (see Table 1).
In order to limit any fault current due to input ESD leakage
current, resistors of up to 5k may be added in series with
the
input.
The effect of series resistance on the converter
accuracy can be evaluated from the curves presented in
the Input Current/Reference Current sections. In addition,
series resistors will introduce a temperature dependent
error due to input leakage current. A 1nA input leakage
current will develop a 1ppm offset error on a 5k resistor
if V
REF
= 5V. This error has a very strong temperature
dependency.
I
2
C INTERFACE
The LTC2489 communicates through an I
2
C interface. The
I
2
C interface is a 2-wire open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be externally
connected to the supply through a pull-up resistor. When
the data line is not being driven, it is high. Data on the
I
2
C bus can be transferred at rates up to 100kbits/s in the
standard mode and up to 400kbits/s in the fast mode. The
V
CC
power should not be removed from the device when
the I
2
C bus is active to avoid loading the I
2
C bus lines
through the internal ESD protection diodes.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when perform
-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
applicaTions inForMaTion
LTC2489
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The LTC2489 can only be addressed as a slave. Once ad-
dressed, it can receive channel selection bits or transmit
the last
conversion result. The serial clock line, SCL, is
always an input to the LTC2489 and the serial data line
SDA is bidirectional. The device supports the standard
mode and the fast mode for data transfer speeds up to
400kbits/s. Figure 2 shows the definition of the I
2
C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit ad
-
dress matches the hard wired, LTC2489’s address (one of
9 pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2489 issues an ACK by pulling the SDA line low.
The LTC2489 has two registers. The output register (24
bits long) contains the last conversion result. The input
register (8 bits long) sets the input channel.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1
µA. When the L
TC2489 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to three
bytes from the LTC2489. After a complete read operation
(3 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
The data output stream is 24 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit
is the conversion result sign bit (SIG) (see Tables 1 and
2). This bit is high if V
IN
≥ 0 and low if V
IN
< 0 (where V
IN
corresponds to the selected input signal IN
+
– IN
). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
SDA
SCL
S Sr P S
t
HD(SDA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(SDA)
t
SP
t
BUF
t
r
t
f
t
r
t
f
t
HIGH
2489 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I
2
C Bus
applicaTions inForMaTion

LTC2489CDE#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit, 4-ch I2C Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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