LTC2489
13
2489fb
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over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below
–FS. The function of these bits is summarized in Table 2.
The 16 bits following the MSB bit are the conversion
result in binary two’
s complement format. The remaining
six bits are always 0.
As long as the voltage on the selected input channels (IN
+
and IN
–
) remains between –0.3V and V
CC
+ 0.3V (absolute
maximum operating range) a conversion result is gener-
ated for any differential input voltage V
IN
from –FS = –0.5
• V
REF
to +FS = 0.5 • V
REF
. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS. For differential input volt
-
ages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
Table 2. LTC2489 Status Bits
Input Range
Bit 23
SIG
Bit 22
MSB
V
IN
≥ FS 1 1
0V ≤ V
IN
< FS 1 0
–FS ≤ V
IN
< 0V 0 1
V
IN
< –FS 0 0
Table 1. Output Data Format
Differential Input Voltage
V
IN
*
Bit 23
SIG
Bit 22
MSB
Bit 21
Bit 20
Bit 19 … Bit 6
LSB
Bits 5-0
Always 0
V
IN
* ≥ FS** 1 1 0 0 0 … 0 000000
FS** – 1LSB 1 0 1 1 1 … 1 000000
0.5 • FS** 1 0 1 0 0 … 0 000000
0.5 • FS** – 1LSB 1 0 0 1 1 … 1 000000
0 1 0 0 0 0 … 0 000000
–1LSB 0 1 1 1 1 … 1 000000
–0.5 • FS** 0 1 1 0 0 … 0 000000
–0.5 • FS** – 1LSB 0 1 0 1 1 … 1 000000
–FS** 0 1 0 0 0 … 0 000000
V
IN
* < –FS** 0 0 1 1 1 … 1 000000
*The differential input voltage V
IN
= IN
+
– IN
–
. **The full-scale voltage FS = 0.5 • V
REF
.
INPUT DATA FORMAT
The LTC2489 serial input is 8 bits long and is written into
the device in one 8-bit word. SGL, ODD, A2, A1, A0 are
used to select the input channel.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN
+
= CH0, IN
–
=
CH1). The first conversion automatically begins at power-
up using this default input channel. Once the conversion
is complete, a new channel may be written into the device.
The first three bits of the input word consist of two pre
-
amble bits and one enable bit. These three bits are used
to enable the input channel selection. V
alid settings for
these three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits
are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence de
-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent chan-
nels can be selected to form a differential input. For SGL
= 1, one of 4 channels is selected as the positive input.
The
negative
input is COM for all single-ended operations.
applicaTions inForMaTion
