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LTC2489CDE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC2489
16
2489fb
For more information www.linear.com/LTC2489
Figure 6. Write, Read, Start Conversion
Figure 7. Start a New Conversion Without Reading Old Conversion Result
applicaTions inForMaTion
Discarding a Conversion Result and Initiating a New
Conversion with Optional Write
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
channel is required, this data can be written into the device
and a Stop command will initiate the next conversion (see
Figure 7).
Synchronizing Multiple LTC2489s with a Global
Address Call
In applications where several LTC2489s (or other I
2
C delta-
sigma ADCs from Linear Technology Corporation) are used
on the same I
2
C bus, all converters can be synchronized
through the use of a global address call. Prior to issuing the
global address call, all converters must have completed a
conversion cycle. The master then issues a Start, followed
by the global address 1110111, and a write request. All
converters will be selected and acknowledge the request.
The master then sends a write byte (optional) followed by
the Stop command. This will update the channel selection
(optional) and simultaneously initiate a start of conversion
for all delta-sigma ADCs on the bus (see Figure 8). In order
to synchronize multiple converters without changing the
channel, a Stop may be issued after acknowledgement of
the global write command. Global read commands are not
allowed and the converters will NAK a global read request.
Figure 8. Synchronize Multiple LTC2489s with a Global Address Call
7-BIT ADDRESS 7-BIT ADDRESSS RW ACK ACKWRITE Sr PREAD
2489 F06
CONVERSION CONVERSIONADDRESSSLEEP DATA OUTPUTDATA INPUT
7-BIT ADDRESSS W ACK WRITE (OPTIONAL) P
2489 F07
CONVERSION CONVERSIONSLEEP DATA INPUT
GLOBAL ADDRESS
SCL
SDA
S W ACK WRITE (OPTIONAL) P
2489 F08
…LTC2489 LTC2489 LTC2489
ALL LTC2489s IN SLEEP CONVERSION OF ALL LTC2489s
DATA INPUT
LTC2489
17
2489fb
For more information www.linear.com/LTC2489
Driving the Input and Reference
The input and reference pins of the LTC2489 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 9.
When using the LTC2489’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/
reference pins. If the total external RC time constant is less
than 580ns the errors introduced by the sampling process
are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs
(CH0-CH3, COM), on the other hand, are typically driven
from larger sour
ce resistances. Source resistances up
to 10k may interface directly to the LTC2489 and settle
completely; however, the addition of external capacitors
at the input terminals in order to filter unwanted noise
(antialiasing) results in incomplete settling.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kW with no external bypass capacitor or up
to 500W with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kW bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2489 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
for buffers.
The switching algorithm forces the average input current
on the positive input (I
IN
+
) to be equal to the average input
current on the negative input (I
IN
–
). Over the complete
conversion cycle, the average differential input current
(I
IN
+
– I
IN
–
) is zero. While the differential input current is
zero, the common mode input current (I
IN
+
+ I
IN
–
)/2 is
proportional to the difference between the common mode
input voltage (V
IN(CM)
) and the common mode reference
voltage (V
REF(CM)
).
applicaTions inForMaTion
IN
+
IN
–
10kΩ
INTERNAL
SWITCH
NETWORK
10kΩ
C
EQ
12µF
10kΩ
I
IN
–
REF
+
I
REF
+
I
IN
+
I
REF
–
2489 F09
SWITCHING FREQUENCY
f
SW
= 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 • f
EOSC
EXTERNAL OSCILLATOR
REF
–
10kΩ
100Ω
INPUT
MULTIPLEXER
100Ω
Figure 9. Equivalent Analog Input Circuit
I IN
+
( )
AVG
= I IN
–
( )
AVG
=
V
IN(CM)
−V
REF(CM)
0.5•R
EQ
I REF
+
( )
AVG
≈
1.5V
REF
+ V
REF(CM)
– V
IN(CM)
( )
0.5•R
EQ
–
V
IN
2
V
REF
•R
EQ
where:
V
REF
=REF
+
−REF
−
V
REF(CM)
=
REF
+
–REF
−
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
V
IN
=IN
+
−IN
−
,WHEREIN
+
ANDIN
−
ARE THE SELECTEDINPUT CHANNELS
V
IN(CM)
=
IN
+
–IN
−
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
R
EQ
=2.98MW INTERNAL OSCILLATOR
R
EQ
= 0.833•10
12
( )
/ f
EOSC
EXTERNAL OSCILLATOR
LTC2489
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2489fb
For more information www.linear.com/LTC2489
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com
-
mon mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
IN(CM)
and V
REF(CM)
. For a reference
common mode voltage of 2.5V and an input common
mode of 1.5V, the common mode input current is ap
-
proximately 0.74µA. This common mode input current
does not degrade the accuracy if the source impedances
tied to IN
+
and IN
–
are matched. Mismatches in source
impedance lead to a fixed offset error but do not effect
the linearity or full-scale reading. A 1% mismatch in a 1k
source resistance leads to a 74µV shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2489, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the dif
-
ference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the ac
-
curacy of the internal oscillator, a one-time calibration will
remove this error.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Reference Current
Similar to the analog inputs, the LTC2489 samples the
differential reference pins (REF
+
and REF
–
) transferring
small amounts of charge to and from these pins, thus pro-
ducing a dynamic reference current. If incomplete settling
occurs (as a function the reference source resistance and
reference bypass capacitance) linearity and gain errors
are introduced.
For relatively small values of external reference capacitance
(C
REF
< 1nF), the voltage on the sampling capacitor settles
for reference impedances of many kW (if C
REF
= 100pF up
to 10kW will not degrade the performance) (see Figures
10 and 11).
In cases where large bypass capacitors are required on
the reference inputs (C
REF
> .01µF), full-scale and linear-
ity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces a
applicaTions inForMaTion
Figure 10. +FS Error vs R
SOURCE
at V
REF
(Small C
REF
) Figure 11. –FS Error vs R
SOURCE
at V
REF
(Small C
REF
)
R
SOURCE
(Ω)
0
50
70
10k
2489 F10
30
10
40
60
80
20
0
–10
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
–
= 1.25V
f
O
= GND
T
A
= 25°C
C
REF
= 0.01µF
C
REF
= 0.001µF
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
(Ω)
0
–FS ERROR (ppm)
–30
–10
10
10k
2489 F11
–50
–70
–40
–20
0
–60
–80
–90
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
–
= 3.75V
f
O
= GND
T
A
= 25°C
C
REF
= 0.01µF
C
REF
= 0.001µF
C
REF
= 100pF
C
REF
= 0pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LTC2489CDE#PBF

Mfr. #:
Buy LTC2489CDE#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit, 4-ch I2C Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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