MAX15023ETG+ Datasheet MAX15023ETG+, MAX15023ETG+T, MAX15023ETG/V+T | P13-P15

MAX15023

Wide 4.5V to 28V Input, Dual-Output

Synchronous Buck Controller

Maxim Integrated

The internal oscillator frequency is divided down to

obtain separated clock signals for each regulator. The

phase difference of the two clock signals is 180°, so that

the high-side MOSFETs turn on out-of-phase. The instan-

taneous input current peaks of both regulators no longer

overlap, resulting in reduced RMS ripple current and

input voltage ripple. As a result, this allows an input

capacitor with a lower ripple-current rating to be used or

allows the use of fewer or less expensive capacitors, as

well as reduces EMI filtering and shielding requirements.

Internal 5.2V Linear Regulator

The MAX15023’s internal functions and MOSFET drivers

are designed to operate from a 5V ±10% supply volt-

age. If the available supply voltage exceeds 5.5V, a

5.2V internal low-dropout linear regulator is used to

power internal functions and the MOSFET drivers at

. If an external 5V ±10% supply voltage is available,

then IN and V

can be tied to the 5V supply. The maxi-

mum regulator input voltage (V

) is 28V. The regulator’s

input (IN) must be bypassed to SGND with a 1µF

ceramic capacitor when the regulator is used. Bypass

the regulator’s output (V

) with a 4.7µF ceramic

capacitor to SGND. The V

dropout voltage is typically

70mV, so when V

is greater than 5.5V, V

is typically

5.2V. The MAX15023 also employs a UVLO circuit that

disables both regulators when V

falls below 3.8V

(typ). The 430mV UVLO hysteresis prevents chattering

on power-up/power-down.

The internal V

linear regulator can source up to

100mA to supply the IC, power the low-side gate dri-

vers, recharge the external boost capacitors, and sup-

ply small external loads. The current available for

external loads depends on the current consumed for

the MOSFET gate drive.

For example, when switched at 600kHz, a single

MOSFET with 18nC total gate charge (at V

= 5V)

requires 18nC x 600kHz ≅ 11mA. Since four MOSFETs

are driven and 6mA (max) is used by the internal con-

trol functions, the current available for external loads is:

(100 – (4 x 11) – 6)mA ≅ 50mA

MOSFET Gate Drivers (DH_, DL_)

The DH_ and DL_ drivers are optimized for driving

large size n-channel power MOSFETs. Under normal

operating conditions and after startup, the DL_ low-side

drive waveform is always the complement of the DH_

high-side drive waveform (with controlled dead time to

prevent cross-conduction or shoot-through). On each

channel, an adaptive dead-time circuit monitors the DH

and DL outputs and prevents the opposite-side

MOSFET from turning on until the other MOSFET is fully

off. Thus, the circuit allows the high-side driver to turn

on only when the DL_ gate driver has been turned off.

Similarly, it prevents the low-side (DL_) from turning on

until the DH_ gate driver has been turned off.

The adaptive driver dead time allows operation without

shoot-through with a wide range of MOSFETs, minimizing

delays, and maintaining efficiency. There must be a low-

resistance, low-inductance path from the DL_ and DH_

drivers to the MOSFET gates for the adaptive dead-time

circuits to work properly. Otherwise, because of the stray

impedance in the gate discharge path, the sense circuit-

ry could interpret the MOSFET gates as off while the V

of the MOSFET is still high. To minimize stray imped-

ance, use very short, wide traces (50 mils to 100 mils

wide if the MOSFET is 1in from the driver).

Synchronous rectification reduces conduction losses in

the rectifier by replacing the normal low-side Schottky

catch diode with a low-resistance MOSFET switch. The

internal pulldown transistor that drives DL_ low is

robust, with a 0.75Ω (typ) on-resistance. This low on-

resistance helps prevent DL_ from being pulled up dur-

ing the fast rise time of the LX_ node, due to capacitive

coupling from the drain to the gate of the low-side syn-

chronous rectifier MOSFET.

High-Side Gate-Drive Supply (BST_)

and Internal Boost Switches

The high-side MOSFET is turned on by closing an inter-

nal switch between BST_ and DH_. This provides the

necessary gate-to-source voltage to turn on the high-side

MOSFET, an action that boosts the gate drive signal

above V

. The boost capacitor connected between

BST_ and LX_ holds up the voltage across the gate dri-

ver during the high-side MOSFET on-time.

The charge lost by the boost capacitor for delivering the

gate charge is refreshed when the high-side MOSFET is

turned off and LX_ node swings down to ground. When

the corresponding LX_ node is low, an internal high-volt-

age switch connected between V

and BST_ recharges

the boost capacitor to the V

voltage. The need for

external boost diodes is negated. See the

Boost Flying-

Capacitor Selection

section in the

Design Procedure

section to choose the right size of the boost capacitor.

Enable Inputs (EN_),

Adaptive Soft-Start and Soft-Stop

The MAX15023 can be used to regulate two indepen-

dent outputs. Each of the two outputs can be turned on

and off independently of one another by controlling the

enable input of each phase (EN1 and EN2).

A logic-high on each enable pin turns on the corre-

sponding channel. Then, the soft-start sequence is initi-

ated by step-wise increasing the reference voltage of

MAX15023

Wide 4.5V to 28V Input, Dual-Output

Synchronous Buck Controller

Maxim Integrated

the error amplifier. The duration of the soft-start ramp is

2048 switching cycles and the resolution is 1/64 of the

steady-state regulation voltage. This allows a smooth

increase of the output voltage. A logic-low on each EN_

initiates a soft-stop sequence by stepping down the ref-

erence voltage of the error amplifier. After the soft-stop

sequence is completed, the MOSFET drivers are both

turned off. See Figure 1 for more detail.

Connect EN1 and EN2 to V

for always-on operation.

Owing to their accurate turn-on and turn–off thresholds,

EN1 and EN2 can be used as a UVLO adjustment input

and for power sequencing together with the PGOOD_

outputs. (See the

Setting the Enable Input (EN_)

section).

The adaptive action in the soft-start becomes visible if

the cycle-by-cycle, low-side, source peak current limit

is reached during the soft-start ramping sequence. In

this case, the rate-of-rise of the internal reference is

decreased, so that the PWM controller tries to regulate

to the inductor current around its limit value, rather than

the output voltage. The soft-start time can be prolonged

up to 4096 clock cycles (twice the normal soft-start

duration). This implementation allows the soft-start time

to be automatically adapted to the time necessary to

keep the LX current below the limit while charging the

output capacitor.

Since soft-start is invoked by the hiccup-mode short-

circuit protection, also see the

Hiccup Mode

Overcurrent Protection

section for additional details.

Power-Good Outputs (PGOOD_)

The MAX15023 includes two power-good comparators

to monitor the regulators’ output voltages and detect

the power-good threshold, fixed at 92.5% of the nomi-

nal FB voltage. The PGOOD_ outputs are open-drain

and should be pulled up with an external resistor to the

supply voltage of the logic input they drive. This voltage

should not exceed 28V. They can sink up to 2mA of

current while low.

2048 CLK

CYCLES

2048 CLK

CYCLES

HIA

UVLO

EN_

OUT_

DAC_VREF_

DH_

DL_

UVLO

Undervoltage threshold value is provided in

the Electrical Characteristics table.

Internal 5.2V linear regulator output.

Active-high enable input.

Regulator output voltage.

Regulator internal soft-start and soft-stop signal.

Regulator high-side gate-driver output.

Regulator low-side gate-driver output.

rising while below the UVLO threshold.

EN_ is low.

EN_

OUT_

DAC_VREF_

DH_

DL_

SYMBOL DEFINITION

is higher than the UVLO threshold. EN_ is low.

EN is pulled high. DH_ and DL_ start switching.

Normal operation.

drops below UVLO.

goes above UVLO threshold. DH_ and DL_

start switching. Normal operation.

EN_ is pulled low. V

OUT_

enters soft-stop.

EN_ is pulled high. DH_ and DL_ start switching.

Normal operation.

drops below UVLO.

SYMBOL DEFINITION

Figure 1. MAX15023 Detailed Power-On/-Off Sequencing

MAX15023

Wide 4.5V to 28V Input, Dual-Output

Synchronous Buck Controller

Maxim Integrated

Each PGOOD_ goes high (high impedance) when the

corresponding regulator output increases above 92.5%

of its nominal regulated voltage. Each PGOOD_ goes

low when the corresponding regulator output voltage

drops typically below 89.5% of its nominal regulated

voltage. PGOOD_ can be used as power-on-reset or

power sequencing for the two regulators.

PGOOD_ asserts low during the hiccup timeout period.

Startup into a Prebiased Output

When the controller starts into a prebiased output, the

DH_/DL_ complementary switching sequence is inhibit-

ed until the PWM comparator commands its first PWM

pulse. Until then, DH_ and DL_ are kept off so that the

converter does not sink current from the output. The

first PWM pulse occurs when the ramping reference

voltage increases above the FB_ voltage or the internal

soft-start time is over.

Current-Limit Circuit (LIM_)

The current-limit circuit employs a cycle-by-cycle low-

side source peak and sink current-sensing algorithm

that uses the on-resistance of the low-side MOSFET as

a current-sensing element, so that costly sense resis-

tors are not required. The current-limit circuit is also

temperature compensated to track the MOSFET’s on-

resistance variation over temperature. The current limit

is adjustable on each channel with an external resistor

at LIM_ (see the

Typical Application Circuits

), and

accommodates MOSFETs with a wide range of on-

resistance characteristics (see the

Design Procedure

section). The adjustment range is from 30mV to 300mV

for the cycle-by-cycle, low-side, source peak current

limit, corresponding to resistor values of 6kΩ to 60kΩ.

The cycle-by-cycle, low-side, source peak current-limit

threshold across the low-side MOSFET is precisely 1/10

the voltage seen at LIM_, while the cycle-by-cycle, low-

side, sink peak current-limit threshold is 1/20 the volt-

age seen at LIM_.

The MAX15023 uses SGND to sense the voltage of the

source terminals of the low-side MOSFETs for both

channels, and LX_ to sense the drain voltage of each

low-side MOSFET. Carefully observe the

PCB Layout

Guidelines

section to ensure that noise and systematic

errors do not corrupt the current-sense signals seen by

LX_ and SGND on each channel.

Cycle-by-cycle, low-side, source peak current limit acts

when the inductor current flows in the normal direction,

and the drain (LX_) is more negative than source

(sensed by SGND) during the low-side MOSFET on-

time. If the magnitude of current-sense signal exceeds

the cycle-by-cycle, low-side, source peak current-limit

threshold during the low-side MOSFET on-time, the

controller does not initiate a new PWM cycle and lets

the inductor current decay in the next cycle. Since

cycle-by-cycle, low-side, source peak current sensing

is employed, the actual peak current is greater than the

current-limit threshold by an amount equal to the induc-

tor ripple current. Therefore, the exact current-limit

characteristic and maximum load capability are func-

tions of the low-side MOSFET’s on-resistance, current-

limit threshold, inductor value, and input voltage.

Cycle-by-cycle, low-side, sink peak current limit is also

implemented by monitoring the voltage drop across the

low-side MOSFET, but with opposite polarity (drain

more positive than source). If this drop exceeds 1/20

the voltage at the corresponding LIM_ pin at any time

during the low-side MOSFET on-time, the low-side

MOSFET is turned off and the inductor current flows

from the output through the high-side MOSFET back. If

the cycle-by-cycle, low-side, sink peak current limit is

activated, the DH_ and DL_ switching sequence is no

longer complementary.

Hiccup Mode Overcurrent Protection

Hiccup mode overcurrent protection reduces power

dissipation during prolonged short-circuit or deep over-

load conditions.

After the soft-start sequence has been completed, on

each switching cycle where the cycle-by-cycle, low-side,

source peak current-limit threshold is reached, a 3-bit

counter is incremented. The counter is decremented on

each switching cycle where the threshold is not reached,

and stopped at zero (000).

If the cycle-by-cycle, low-side, source peak current-

limit condition persists, the counter fills up reaching 111

(= 7 events). Then, the controller stops both DL_ and

DH_ drivers and waits for 7936 switching cycles (hic-

cup timeout delay). After this delay, the controller initi-

ates a new soft-start sequence.

If cycle-by-cycle, low-side, source peak current-limit

events occur during the soft-start time, turn-on cycles are

still skipped to control the inductor current, but the fill-up

of the 3-bit counter does not terminate the soft-start

sequence. Rather, the soft-start ramp is slowed down or

rolled back based on the cycle-by-cycle, low-side, source

peak current-limit events occurrences, so that the PWM

controller tries to regulate the inductor current around its

limit value, rather than the output voltage.

This proprietary technique prevents the duty cycle from

saturating, and limits the on-time and thus, the peak

inductor current is reached every time the high-side

MOSFET is turned on.

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MAX15023ETG+

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Manufacturer:

Maxim Integrated

Description:

Switching Controllers 4.5-28V Input Dual Out Synch Buck

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MAX15023ETG+

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