MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
19
Maxim Integrated
The output voltage ripple as a consequence of the ESR
and the output capacitance is:
where I
L
is the peak-to-peak inductor current ripple
(see the
Inductor Selection
section). These equations
are suitable for initial capacitor selection, but final val-
ues should be verified by testing in a prototype or eval-
uation circuit.
As a general rule, a smaller inductor ripple current
results in less output ripple voltage. The output capaci-
tor must be also checked against load-transient
response requirements. The allowable deviation of the
output voltage during fast load transients also deter-
mines the output capacitance, its ESR, and its equiva-
lent series inductance (ESL). The output capacitor
supplies the load current during a load step until the
controller responds with a greater duty cycle. The
response time (t
RESPONSE
) depends on the closed-
loop bandwidth of the converter (see the
Compensation
section). The resistive drop across the output capaci-
tor’s ESR, the drop across the capacitor’s ESL (V
ESL
),
and the capacitor discharge causes a voltage droop
during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic or polymer and ceramic capacitors for better
transient load and voltage ripple performance. Non-
leaded capacitors and capacitors in parallel help
reduce the ESL. Keep the maximum output voltage
deviation below the tolerable limits of the load. Use the
following equations to calculate the required ESR, ESL,
and capacitance value during a load step:
where I
STEP
is the load step, t
STEP
is the rise time of the
load step, t
RESPONSE
is the response time of the con-
troller, and f
O
is the closed-loop crossover frequency.
Compensation
Each channel of the MAX15023 provides an internal
transconductance amplifier with its inverting input and
its output available to the user for external frequency
compensation. The flexibility of external compensation
for each converter offers wide selection of output filter-
ing components, especially the output capacitor. For
cost-sensitive applications, use low-ESR aluminum
electrolytic capacitors; for component-size sensitive
applications, use low-ESR tantalum, polymer, or ceram-
ic capacitors at the output. The high switching frequen-
cy of the MAX15023 allows use of ceramic capacitors
at the output. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin.
To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero crossover
frequency, and the type of the output capacitor must be
determined.
In a buck converter, the LC filter in the output stage
introduces a pair of complex poles at the following fre-
quency:
The output capacitor and its ESR also introduce a zero
at:
The loop-gain crossover frequency (f
O
, where the loop
gain equals 1 (0dB)) should be set below 1/10 the
switching frequency:
Choosing a lower crossover frequency might also help
in reducing the effects of noise pickup into the feed-
back loop, such as jittery duty cycle.
In order to maintain a stable system, two stability crite-
ria must be met:
1) The phase shift at the crossover frequency f
O
, must
be less than 180°. In other words, the phase margin
of the loop must be greater than zero.
2) The gain at the frequency where the phase shift is
-180° (gain margin) must be less than 1.
f
f
O
SW
10
f
ESR C
ZO
OUT
=
××
1
2π
f
LC
PO
OUT OUT
=
××
1
2π
ESR
V
I
C
It
V
ESL
Vt
I
t
f
ESR
STEP
OUT
STEP RESPONSE
Q
ESL STEP
STEP
RESPONSE
O
=
=
×
=
×
×
1
3
∆∆
V I ESR
V
I
Cf
I
VV V
Vf L
ESR L
Q
L
OUT SW
L
IN OUT OUT
IN SW
=
××
=
×
××
8
()
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
20
Maxim Integrated
It is recommended to have a phase margin around
+50° to +60° to maintain a robust loop stability and
well-behaved transient response.
If an electrolytic or large-ESR tantalum output capacitor
is used, the capacitor ESR zero f
ZO
typically occurs
between the LC poles and the crossover frequency f
O
(f
PO
< f
ZO
< f
O
). In this case, use a Type II (PI or pro-
portional-integral) compensation network.
If a ceramic or low-ESR tantalum output capacitor is
used, the capacitor ESR zero typically occurs above
the desired crossover frequency f
O
, that is f
PO
< f
O
<
f
ZO
. In this situation, choose a Type III (PID or propor-
tional-integral-derivative) compensation network.
Type II Compensation Network
(See Figure 4)
If f
ZO
is lower than f
O
and close to f
PO
, the phase lead
of the capacitor ESR zero almost cancels the phase
loss of one of the complex poles of the LC filter around
the crossover frequency. Therefore, a Type II compen-
sation network with a midband zero and a high-fre-
quency pole can be used to stabilize the loop. In Figure
4, R
F
and C
F
introduce a midband zero (f
Z1
). R
F
and
C
CF
in the Type II compensation network also provide a
high-frequency pole (f
P1
), which mitigates the effects of
the output high-frequency ripple.
To calculate the component values for Type II compen-
sation network in Figure 4, follow the instruction below:
1) Calculate the gain of the modulator (Gain
MOD
)—
composed of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:
where V
IN
is the regulator’s input voltage, V
OSC
is the
amplitude of the ramp in the pulse-width modulator,
V
FB
is the FB_ input voltage set-point (0.6V typically,
see
Electrical Characteristics
table), and V
OUT
is the
desired output voltage.
The gain of the error amplifier (Gain
EA
) in midband fre-
quencies is:
where g
m
is the transconductance of the error amplifier.
The total loop gain as the product of the modulator gain
and the error amplifier gain at f
O
should equal 1. So:
Therefore:
Solving for R
F
:
2) Set a midband zero (f
Z1
) at 0.75 x f
PO
(to cancel
one of the LC poles):
Solving for C
F
:
3) Place a high-frequency pole at f
P1
= 0.5 x f
SW
(to
attenuate the ripple at the switching frequency, f
SW
)
and calculate C
CF
using the following equation:
C
Rf
C
CF
FSW
F
=
××
1
1
π
C
Rf
F
FPO
=
×× ×
1
2075π .
f
RC
f
Z
FF
PO1
1
2
075=
××
π
.
R
VfLV
V V g ESR
F
OSC O OUT OUT
FB IN m
=
×××
()
×
×××
2π
V
V
ESR
fL
V
V
gR
IN
OSC O OUT
FB
OUT
mF
×
××
×××=
()2
1
π
Gain Gain
MOD EA
×=1
Gain g R
EA m F
Gain
V
V
ESR
fL
V
V
MOD
IN
OSC O OUT
FB
OUT
××
()
×
2π
V
REF
R
1
V
OUT
R
2
g
m
R
F
COMP
C
F
C
CF
Figure 4. Type II Compensation Network
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
21
Maxim Integrated
Type III Compensation Network
(See Figure 5)
If the output capacitor used is a low-ESR tantalum or
ceramic type, the ESR-induced zero frequency is usual-
ly above the targeted zero crossover frequency (f
O
). In
this case, Type III compensation is recommended.
Type III compensation provides three poles and two
zeros at the following frequencies:
Two midband zeros (f
Z1
and f
Z2
) cancel the pair of
complex poles introduced by the LC filter:
f
P1
= 0
f
P1
introduces a pole at zero frequency (integrator) for
nulling DC output voltage errors:
Depending on the location of the ESR zero (f
ZO
), f
P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple:
f
P3
attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such
that the phase margin peaks around f
O
.
Ensure that R
F
>>2/g
m
(1/g
m
(MIN) = 1/600µS = 1.67k)
and the parallel resistance of R
1
, R
2
, and R
I
is greater
than 1/g
m
. Otherwise, a 180° phase shift is introduced
to the response and will make it unstable.
The following procedure is recommended:
1) With R
F
10k, place the first zero (f
Z1
) at 0.5 x
f
PO
:
so:
2) The gain of the modulator (Gain
MOD
)—composed of
the regulator’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry at
crossover frequency is:
The gain of the error amplifier (Gain
EA
) in midband fre-
quencies is:
The total loop gain as the product of the modulator gain
and the error amplifier gain at f
O
should be equal to 1.
So:
Therefore:
Solving for C
I
:
3) If f
PO
< f
O
< f
ZO
< f
SW
/2, the second pole (f
P2
)
should be used to cancel f
ZO
. This way, the Bode
plot of the loop gain plot does not flatten out soon
after the 0dB crossover, and maintains its
-20dB/decade slope up to 1/2 the switching frequen-
cy. This is likely to occur if the output capacitor is a
low-ESR tantalum or polymer. Then set:
f
P2
= f
ZO
If a ceramic capacitor is used, then the capacitor ESR
zero, f
ZO
, is likely to be located even above 1/2 the
switching frequency, that is, f
PO
< f
O
< f
SW
/2 < f
ZO
. In
this case, the frequency of the second pole (f
P2
) should
be placed high enough in order not to significantly
erode the phase margin at the crossover frequency. For
example, it can be set at 5 x f
O
, so that its contribution
to phase loss at the crossover frequency, f
O
, is only
about 11°:
f
P2
= 5 x f
O
Once f
P2
is known, calculate R
I
:
R
fC
I
PI
=
××
1
2
2
π
C
VfLC
VR
I
OSC O OUT OUT
IN F
=
××× ×
()
×
2π
V
V
fC L
fCR
IN
OSC
O OUT OUT
OIF
×
×× ×
× ××× =
1
2
21
2
()
π
π
Gain Gain
MOD EA
×=1
Gain f C R
EA O I F
= ×××2π
Gain
V
V
fL C
MOD
IN
OSC
O OUT OUT
×× ×
1
2
2
()π
C
Rf
F
FPO
=
×× ×
1
205π .
f
RC
f
Z
FF
PO1
1
2
05=
××
π
.
f
R
CC
CC
P
F
FCF
FCF
3
1
2
=
××
×
+
π
f
RC
P
II
2
1
2
=
××π
f
RC
f
CRR
Z
FF
Z
II
1
2
1
1
2
1
2
=
××
=
×× +
π
π ()

MAX15023ETG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers 4.5-28V Input Dual Out Synch Buck
Lifecycle:
New from this manufacturer.
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