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MAX15023ETG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
16
Maxim Integrated
In case of a nonideal short circuit applied at the output,
the output voltage equals the output impedance times the
limited inductor current during this phase. After reaching
the maximum allowable limit of the soft-start duration
(twice the normal soft-start time), the controller remains off
for 7936 clock cycles before trying to soft-start again.
Undervoltage Lockout
The MAX15023 has an internal undervoltage lockout
(UVLO) circuit to monitor the voltage on V
CC
. The
UVLO circuit prevents the MAX15023 from operating if
the voltages for the MOSFET drivers or for the internal
control functions are too low. The V
CC
falling threshold
is 3.8V (typ), with 430mV hysteresis to prevent chatter-
ing on the rising/falling edge of the supply voltage.
Before V
CC
reaches UVLO rising threshold voltage,
DL_ and DH_ stay low to inhibit switching.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation
in the MAX15023. When the device’s die-junction tem-
perature exceeds T
J
= +150°C, an on-chip thermal sen-
sor shuts down the device, forcing DL_ and DH_ low,
allowing the IC to cool. The thermal sensor turns the
device on again after the junction temperature cools by
20°C. During thermal shutdown, the regulators shut
down, and soft-start is reset. Thermal-overload protection
can be triggered by power dissipation in the LDO regula-
tor, by excessive driving losses, or by both. Therefore,
carefully evaluate the total power dissipation (see the
Power Dissipation
section) to avoid unwanted triggering
of the thermal-overload protection in normal operation.
Design Procedure
Effective Input Voltage Range
Although the MAX15023 controllers can operate from
input supplies up to 28V and regulate down to 0.6V, the
minimum voltage conversion ratio (V
OUT
/V
IN
) might be
limited by the minimum controllable on-time. For proper
fixed-frequency PWM operation, the voltage conversion
ratio should obey the following condition:
where t
ON(MIN)
is 100ns (max) and f
SW
is the switching
frequency in Hertz. If the desired voltage conversion
does not meet the above condition, then pulse skipping
occurs to decrease the effective duty cycle. To avoid
this, decrease the switching frequency or lower the
input voltage V
IN
.
The maximum voltage conversion ratio is limited by the
maximum duty cycle (D
max
):
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistances. V
DROP2
is the
sum of the voltage drops in the charging path, includ-
ing high-side switch, inductor, and PCB resistances. In
practice, the above condition should be met with ade-
quate margin for good load-transient response.
Setting the Enable Input (EN_)
Each controller has an enable input referenced to an
analog voltage (1.2V). When the voltage exceeds 1.2V,
the regulator is enabled. To set a specific turn-on
threshold that can act as a secondary UVLO, a resistive
divider circuit can be used (see Figure 2)
Select R
2
(EN_ to SGND resistor) to a value lower than
200kΩ. Calculate R
1
(V
MON
to EN_ resistor) with the fol-
lowing equation:
where V
EN_H_
= 1.2V (typical).
RR
V
V
MON
EN H
12
1=
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−
__
V
V
D
D V (1 D ) V
V
OUT
IN
max
max DROP2 max DROP1
IN
<
×+ ×
−
−
V
V
tf
OUT
N
ON(MIN) SW
I
>×
EN_
R
1
V
MON
R
2
MA15023
Figure 2. Adjustable Enable Voltage
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
17
Maxim Integrated
Setting the Output Voltage
Set the MAX15023 output voltage on each channel by
connecting a resistive divider from the output to FB_ to
SGND (Figure 3). Select R
2
(FB_ to SGND resistor) less
than or equal to 16kΩ. Calculate R
1
(OUT_ to FB_ resis-
tor) with the following equation:
where V
FB_
= 0.6V (typ) (see the
Electrical Characteristics
table) and V
OUT_
can range from 0.6V to (0.85 x V
IN
).
Resistor R
1
also plays a role in the design of the Type
III compensation network. If a Type III compensation
network is used, make sure to review the values of R
1
and R
2
according to the
Type III Compensation
Network (See Figure 5)
section.
Setting the Switching Frequency
The switching frequency, f
SW
, for each channel is set
by a resistor (R
T
) connected from RT to SGND. The
relationship between f
SW
and R
T
is:
where f
SW
is in kHz, R
T
is in kΩ, and 24806 is in
1/farad. For example, a 600kHz switching frequency is
set with R
T
= 27.05kΩ. Higher frequencies allow
designs with lower inductor values and less output
capacitance. Consequently, peak currents and I
2
R
losses are lower at higher switching frequencies, but
core losses, gate-charge currents, and switching loss-
es increase.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX15023: inductance value (L),
inductor saturation current (I
SAT
), and DC resistance
(R
DC
). To select inductance value, the ratio of inductor
peak-to-peak AC current to DC average current (LIR)
must be selected first. A good compromise between
size and loss is a 30% peak-to-peak ripple current to
average-current ratio (LIR = 0.3). The switching fre-
quency, input voltage, output voltage, and selected LIR
then determine the inductor value as follows:
where V
IN
, V
OUT
, and I
OUT
are typical values (so that
efficiency is optimum for typical conditions). The
switching frequency is set by R
T
(see the
Setting the
Switching Frequency
section). The exact inductor value
is not critical and can be adjusted in order to make
trade-offs among size, cost, efficiency, and transient
response requirements. Lower inductor values minimize
size and cost, but also improve transient response and
reduce efficiency due to higher peak currents. On the
other hand, higher inductance increases efficiency by
reducing the RMS current, but requires more output
capacitance to meet load-transient specifications.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The
inductor’s saturation rating (I
SAT
) must be high enough
to ensure that saturation can occur only above the max-
imum current-limit value, given the tolerance of the low-
side MOSFET’s on-resistance and of the LIM_ reference
current (I
LIM
). On the other hand, these tolerances
should not prevent the converter from delivering the
rated load current (I
LOAD(MAX)
). Combining these con-
ditions, the inductor saturation current (I
SAT
) should be
such that:
where R
DS(ON,MAX)
and R
DS(ON,TYP)
are the maximum
and typical on-resistance of the low-side MOSFET. For
a given inductor type and value, choose the LIR corre-
sponding to the worst-case inductor tolerance.
For LIR = 0.4, and a +25% on the low-side MOSFET’s
R
DS(ON,MAX)
, the inductor saturation current should be
about 50% greater than the converter’s maximum load
current. A variety of inductors from different manufac-
turers can be chosen to meet this requirement (for
example, Coilcraft MSS1278 series).
I1I
SAT
R
DS(ON,MAX)
R
DS(ON,TYP)
LOAD(MAX)
>×+
⎛
⎝
⎜
⎞
⎠
⎟
×
LIR
2
L
VVV
V f I LIR
OUT IN OUT
IN SW OUT
=
−()
R
f
T
SW
=
24806
1 0663
()
.
RR
V
V
OUT
FB
12
1=
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−
_
_
FB_
R
1
OUT_
R
2
MA15023
Figure 3. Adjustable Output Voltage
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
18
Maxim Integrated
Setting the Cycle-by-Cycle, Low-Side,
Source Peak Current Limit
The minimum current-limit threshold must be high
enough to support the maximum expected load current
with the worst-case low-side MOSFET on-resistance
value since the low-side MOSFET’s on-resistance is
used as the current-sense element. The inductor’s
cycle-by-cycle, low-side, source peak current occurs at
I
LOAD(MAX)
minus half the ripple current. The ripple cur-
rent is maximum when the inductor value is at the lower
limit of its specified tolerance. The minimum value of
the current-limit threshold voltage (V
ITH
) should be
greater than the voltage on the low-side MOSFET dur-
ing the ripple-current valley:
where R
DS(ON)
is the on-resistance of the low-side
MOSFET in ohms. Use the maximum value for R
DS(ON)
from the low-side MOSFET’s data sheet.
To adjust the current-limit threshold, connect a resistor
(R
LIM_
) from LIM_ to SGND. The relationship between
the current-limit threshold (V
ITH_
) and R
LIM_
is:
where R
LIM_
is in kΩ and V
ITH_
is in mV.
An R
LIM_
resistance range of 6kΩ to 60kΩ corresponds
to a current-limit threshold of 30mV to 300mV. When
adjusting the current limit, use 1% tolerance resistors to
minimize errors in the current-limit threshold setting.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The two converters of the MAX15023 run 180° out-of-
phase, thereby, effectively doubling the switching fre-
quency at the input and lowering the input RMS current.
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle between
converter 1 and converter 2. In fact, the worst-case input
RMS current occurs when only one controller is operat-
ing. The converter delivering the highest output power
(V
OUT
x I
OUT
) must be used in the formulas below:
The input capacitor RMS current requirement (I
RMS
) is
defined by the following equation:
I
RMS
has a maximum value when the input voltage
equals twice the output voltage (V
IN
= 2V
OUT
), so
I
RMS(MAX)
= I
LOAD(MAX)
/2.
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
long-term reliability.
The input voltage ripple is composed of ∆V
Q
(caused
by the capacitor discharge) and ∆V
ESR
(caused by the
ESR of the capacitor). Use low-ESR ceramic capacitors
with high ripple current capability at the input. Assume
the contribution from the ESR and capacitor discharge
are equal to 50%. Calculate the input capacitance and
ESR required for a specified input voltage ripple using
the following equations:
where:
and:
where:
All equations listed above are valid under the assump-
tion that the input ports of both converters can be
merged in the physical layout, so that only one input
capacitor truly serves both converters. If this is not the
case, additional low-ESR, low-ESL ceramic capacitors
should be locally placed on each converter’s input port,
connected between the drain of the high-side MOSFET
and the source of the low-side MOSFET.
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt-
age, and transient response. The output ripple has two
components: variations in the charge stored in the out-
put capacitor, and the voltage drop across the capaci-
tor’s ESR caused by the current flowing into and out of
the capacitor:
∆∆∆VVV
RIPPLE ESR Q
≅+
D
V
V
OUT
IN
=
C
IDD
Vf
IN
OUT
QSW
=
×
×
−()1
∆
∆I
VV V
Vf L
L
IN OUT OUT
IN SW
=
×
××
−()
ESR
V
I
I
IN
ESR
OUT
L
=
+
∆
∆
2
II
VVV
V
RMS LOAD MAX
OUT IN OUT
IN
=
−
()
()
R
V
A
LIM
ITH
_
_
=
×10
50µ
VR I
LIR
ITH DS ON MAX LOAD MAX
>××
⎛
⎝
⎜
⎞
⎠
⎟
−
(, ) ( )
1
2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

MAX15023ETG+

Mfr. #:
Buy MAX15023ETG+
Manufacturer:
Maxim Integrated
Description:
Switching Controllers 4.5-28V Input Dual Out Synch Buck
Lifecycle:
New from this manufacturer.
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