DS5003
Secure Microprocessor Chip
10 ______________________________________________________________________________________
0
ALE
CLOCK
DATA OUT
WRITE TO SBUF REGISTER
INPUT DATA
1 2 3 4 5 6 7 8
CLEAR RI
VALID
01234567
t
SPCLK
t
CHDIV
t
DOCH
t
CHDO
t
CHDV
VALID VALID VALID VALID VALID VALID
SET RI
SET TI
Figure 5. Serial Port Timing (Mode 0)
1
XTAL2
ALE
BA0–BA14 PC OUT
DATA IN DATA IN DATA IN DATA DATA OUT
PC OUT PC OUT PC OUTDPL AND (DPH OR P2 SFR OUT) DPL AND (DPH OR P2 SFR OUT)
BD0–BD7
CE1, CE2,
OR CE1N
CE1, CE2, CE3,
CE4, PE1, PE2,
PE3, PE4, OR CE1N
R/W
2 3 4 5 6 1 2 3 4 5 6 6 1 2 3 4 5 6
MACHINE CYCLE MACHINE CYCLE MACHINE CYCLE
t
CEL1LPA
t
OVCE1H
t
DACEH
t
CE1HOV
t
CEHDV
t
RWLDV
t
RWHDV
t
CEHDV
t
CEL1HPA
t
CELDA
t
CEHDA
t
AVRWL
t
RWLPW
t
CEHDA
t
CELDA
t
CEPW
t
CEPW
Figure 6. Byte-Wide Bus Timing
DS5003
Secure Microprocessor Chip
______________________________________________________________________________________ 11
READ OPERATION
DATA VALID
t
AR
t
RR
t
RD
t
AD
t
RA
t
RDZ
CS OR A0
RD
DATA
WRITE OPERATION
DATA VALID
t
AW
t
WW
t
WD
t
DW
t
WA
CS OR A0
DATA
WR
RD
DMA
t
ACD
t
ACC
t
ACC
t
CRQ
t
CRQ
t
CAC
t
CAC
DATA VALID VALID
DRQ
DACK
WR
Figure 7. RPC Timing Mode
DS5003
Secure Microprocessor Chip
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
POWER PINS
13 V
CC
Power Supply, +5V
12 V
CCO
V
CC
Output. This is switched between V
CC
and V
LI
by internal circuits based on the level of V
CC
.
When power is above the lithium input, power is drawn from V
CC
. The lithium cell remains
isolated from a load. When V
CC
is below V
LI
, V
CCO
switches to the V
LI
source. V
CCO
should be
connected to the V
CC
pin of an SRAM.
54 V
LI
Lithium Voltage Input. Connect to a lithium cell greater than V
LIMIN
and no greater than V
LIMAX
as shown in the electrical specifications. Nominal value is +3V.
52 GND Logic Ground
GENERAL-PURPOSE I/O PINS
11 P0.0/AD0
9 P0.1/AD1
7 P0.2/AD2
5 P0.3/AD3
1 P0.4/AD4
79 P0.5/AD5
77 P0.6/AD6
75 P0.7/AD7
General-Purpose I/O Port 0. This port is open drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this
mode, it does not require pullups.
15 P1.0
17 P1.1
19 P1.2
21 P1.3
25 P1.4
27 P1.5
29 P1.6
31 P1.7
General-Purpose I/O Port 1
49 P2.0/A8
50 P2.1/A9
51 P2.2/A10
56 P2.3/A11
58 P2.4/A12
60 P2.5/A13
64 P2.6/A14
66 P2.7/A15
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus.
36 P3.0/RXD
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART.
This pin should not be connected directly to a PC COM port.
38 P3.1/TXD
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART.
This pin should not be connected directly to a PC COM port.
39 P3.2/INT0 General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
40 P3.3/INT1 General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
41 P3.4/T0 General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
44 P3.5/T1 General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
45 P3.6/WR General-Purpose I/O Port Pin 3.6. Also serves as the write strobe for expanded bus operation.
46 P3.7/RD General-Purpose I/O Port Pin 3.7. Also serves as the read strobe for expanded bus operation.

DS5003FPM-16+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Microprocessors - MPU Soft MCU Chip
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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