NCV7608
www.onsemi.com
10
Table 1. DIGITAL INTERFACE CHARACTERISTICS
Characteristic Symbol Conditions Min Typ Max Unit
Digital Input High Threshold VINH 2.0 − − V
Digital Input Low Threshold VINL − − 0.6 V
Input Pulldown Resistance
(EN, SI, SCLK, IN5, IN6, IN7, IN8)
RPDx EN = SI = SCLK = V
CC
,
IN5 = IN6 = IN7 = IN8 = V
CC
50 100 200
kW
Input Pullup Resistance (CSB) IPUCSB CSB = 0 V 50
100
200
kW
CSB Leakage to V
CC
ILCSx CSB = 5 V, V
CC
= 0 V − − 10
mA
Input Capacitance (Note 12) CINx Not ATE Tested − − 15 pF
SO – Output High VOUTH I(out) = −1 mA V
CC
− 1.0 − − V
SO – Output Low VOUTL I(out) = 1.6 mA − − 0.4 V
SO Tristate Leakage ILSOx CSB = V
CC
−10 − 10
mA
SO Tristate Input Capacitance
(Note 12)
CSOx Not ATE Tested − − 15 pF
SCLK Frequency CLKf V
CC
= 5 V
V
CC
= 3.3 V
−
−
−
−
5
2
MHz
SCLK Clock Period CLKper V
CC
= 5 V
V
CC
= 3.3 V
200
500
−
−
−
−
ns
ns
SCLK High Time CLKH V
CC
= 5 V, Figure 10 85 − − ns
SCLK Low Time CLKL V
CC
= 5 V, Figure 10 85 − − ns
SCLK Setup Time
CLKsup
V
CC
= 5 V, Figure 10 85 − − ns
SI Setup Time Sisup V
CC
= 5 V, Figure 10 50 − − ns
SI Hold Time SIH V
CC
= 5 V, Figure 10 50 − − ns
CSB Setup Time Cssup V
CC
= 5 V, Figure 10 100 − − ns
CSB High Time CSH V
CC
= 5 V, Figure 10 200 − − ns
SO enable after CSB falling edge
(Note 12)
CStSOf V
CC
= 5 V, Figure 10 − − 50 ns
SO disable after CSB rising edge
(Note 12)
CStSOr V
CC
= 5 V, Figure 10 − − 50 ns
SO Rise Time SOR V
CC
= 5 V, C
load
= 40 pF − − 25 ns
SO Fall Time SOF V
CC
= 5 V, C
load
= 40 pF − − 25 ns
SO Valid Time (Note 12) SOV V
CC
= 5 V, C
load
= 40 pF,
Figure 10
− − 50 ns
EN Low Valid Time ENL 10 − −
ms
EN Delay Time END V
CC
= INx = 5 V
EN going high 50% to OUT5 −
OUT8 turning on 50%.
− − 100
ms
SPI wake up after EN rising edge SPIWak SI = 5 V, CSB = 0 V, SCLK =
10 MHz, EN going high 50%
to SO going high 50%,
Figure 9
− − 200
ms
12.Not subject to production testing.
