ADG731BSUZ Datasheet ADG731BSUZ, ADG725BSUZ, ADG731BCPZ | P7-P9

ADG725/ADG731

–7–

PIN CONFIGURATIONS

PIN FUNCTION DESCRIPTIONS

ADG725 ADG731 Mnemonic Function

1–12, 25–40, 1–12, 25–40, Sxx Source. May be an input or output.

45–48 45–48

13, 14 13, 14 V

Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V

and a dual supply of ± 2.5 V.

17 17 SYNC Active Low Control Input. This is the frame synchronization signal for the input

data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input

Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the

falling edges of the following clocks. After eight falling clock edges, switch conditions

are automatically updated. SYNC may be used to frame the signal or just pulled low

for a short period of time to enable the counter and input buffers.

18 18 DIN Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling

edge of the serial clock input.

19 19 SCLK Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of

the serial clock input. These devices can accommodate serial input rates of up to 30 MHz.

23 23 GND Ground Reference

24 24 V

Most Negative Power Supply in a Dual-Supply Application. In single-supply applications,

connect to GND.

41, 43 N/A DA, DB Drain. May be an input or output.

N/A 43

&1"%

Drain. May be an input or output.

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48-Lead LFCSP and TQFP

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

S28

S27

S26

S25

S24

S23

S22

S12

S11

S10

N,C = NO7,17(51$//< CONNECT

S21

S20

S19

S18

ADG731

S17

S13

S14

S15

S16

N,C

S32

S31

S30

S29

N,C

SYNC

DIN

SCLK

N,C

GND

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 39 38 3743 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

S12B

S11B

S10B

S9B

S8B

S7B

S6B

S12A

S11A

S10A

S9A

S8A

S7A

S6A

N,C = NO7 ,17(51$//<CONNECT('

7+((;326('3$',6&211(&7(',17(51$//<

)25,1&5($6('5(/,$%,/,7<2)7+(62/'(5

-2,176$1'0$;,0807+(50$/&$3$%,/,7<,7

,65(&200(1'('7+$77+(3$'%(

62/'(5('727+(68%675$7(,9



S5A

S4A

S3A

S2A

S5B

S4B

S3B

S2B

ADG725

S1A

S1B

S13A

S14A

S15A

S16A

N,C

S16B

S15B

S14B

S13B

N,C

SYNC

DIN

SCLK

N,C

GND

REV. B

–8–

ADG725/ADG731

Table I. ADG725 Truth Table

A3 A2 A1 A0 EN CSA CSB Switch Condition

X X X X X 1 1 Retains Previous Switch Condition

X X X X 1 X X All Switches OFF

0 0 0 0 0 0 0 S1A – DA, S1B – DB

0 0 0 1 0 0 0 S2A – DA, S2B – DB

0 0 1 0 0 0 0 S3A – DA, S3B – DB

0 0 1 1 0 0 0 S4A – DA, S4B – DB

0 1 0 0 0 0 0 S5A – DA, S5B – DB

0 1 0 1 0 0 0 S6A – DA, S6B – DB

0 1 1 0 0 0 0 S7A – DA, S7B – DB

0 1 1 1 0 0 0 S8A – DA, S8B – DB

1 0 0 0 0 0 0 S9A – DA, S9B – DB

1 0 0 1 0 0 0 S10A – DA, S10B – DB

1 0 1 0 0 0 0 S11A – DA, S11B – DB

1 0 1 1 0 0 0 S12A – DA, S12B – DB

1 1 0 0 0 0 0 S13A – DA, S13B – DB

1 1 0 1 0 0 0 S14A – DA, S14B – DB

1 1 1 0 0 0 0 S15A – DA, S15B – DB

1 1 1 1 0 0 0 S16A – DA, S16B – DB

X = Don’t Care

Table II. ADG731 Truth Table

A4 A3 A2 A1 A0 EN CSA Switch Condition

X X X X X X 1 Retains Previous Swi tch Condition

X X X X X 1 X All Switches OFF

00000 0 0 1

00001 0 0 2

00010 0 0 3

00011 0 0 4

00100 0 0 5

00101 0 0 6

00110 0 0 7

00111 0 0 8

01000 0 0 9

01001 0 0 10

01010 0 0 11

01011 0 0 12

01100 0 0 13

01101 0 0 14

01110 0 0 15

01111 0 0 16

10000 0 0 17

10001 0 0 18

10010 0 0 19

10011 0 0 20

10100 0 0 21

10101 0 0 22

10110 0 0 23

10111 0 0 24

11000 0 0 25

11001 0 0 26

11010 0 0 27

11011 0 0 28

11100 0 0 29

11101 0 0 30

11110 0 0 31

11111 0 0 32

X = Don’t Care

REV. B

ADG725/ADG731

–9–

TERMINOLOGY

Most Positive Power Supply Potential.

Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.

Positive Supply Current.

Negative Supply Current.

GND Ground (0 V) Reference.

S Source Terminal. May be an input or output.

DDrain Terminal. May be an input or output.

) Analog Voltage on Terminals D, S.

Ohmic Resistance between D and S.

⌬R

On Resistance Match between any Two Channels.

FLAT(ON)

Flatness is defined as the difference between the maximum and mini mum value of on resistance,

as measured over the specified analog signal range.

(OFF) Source Leakage Current with the Switch OFF.

(OFF) Drain Leakage Current with the Switch OFF.

, I

(ON) Channel Leakage Current with the Switch ON.

INL

Maximum Input Voltage for Logic 0.

INH

Minimum Input Voltage for Logic 1.

INL

INH

) Input Current of the Digital Input.

(OFF) OFF Switch Source Capacitance. Measured with reference to ground.

(OFF) OFF Switch Drain Capacitance. Measured with reference to ground.

(ON) ON Switch Capacitance. Measured with reference to ground.

Digital Input Capacitance.

TRANSITION

Delay time measured between the 50% points of the eighth clock falling edge and 90% points of the output

when switching from one address state to another.

OFF time measured between the 80% points of both switches when switching from one address state to another.

Charge Injection A measure of the glitch impulse transferred from the di gital input to the analog output during switching.

OFF Isolation A measure of unwanted signal coupling through an OFF switch.

Crosstalk A measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance.

On Response The Frequency Response of the ON Switch.

Insertion Loss The Loss Due to the On Resistance of the Switch.

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ADG731BSUZ

Mfr. #:

Buy ADG731BSUZ

Manufacturer:

Analog Devices Inc.

Description:

Multiplexer Switch ICs 32:1 18MHz 4 Ohm Serially Controlled

Lifecycle:

New from this manufacturer.

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ADG731BSUZ

ADG731BSUZ

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