AR0330CM
www.onsemi.com
21
Figure 16 shows the definition of clock jitter for both the
period and the cycle-to-cycle jitter.
Figure 16. Clock Jitter
t
LCLK
t
HCLK
t
pw
t
CKJIT
(RMS)
Period Jitter (t
CKJIT
) is defined as the deviation of the
instantaneous clock t
PW
from an ideal 1 UI. This should be
measured for both the clock high period variation Dt
HCLK,
and the clock low period variation Dt
LCLK
taking the RMS
or 1-sigma standard deviation and quoting the worse case
jitter between Dt
HCLK
and Dt
LCLK
.
Cycle-to-cycle jitter (t
CYCJIT
) is defined as the difference
in time between consecutive clock high and clock low
periods t
HCLK
and t
LCLK
, quoting the RMS value of the
variation D(t
HCLK
− t
LCLK
).
If pk-pk jitter is also measured, this should be limited to
±3-sigma.
Table 24. HiVCM ELECTRICAL AC SPECIFICATION
Symbol
Parameter Min Max Unit
1/UI
Data Rate (Note 1)
280 700 Mbps
t
PW
Bitrate Period (Note 1)
1.43 3.57 ns
t
PRE
Max Setup Time from Transmitter (Notes 1, 2)
0.3 − UI
t
POST
Max Gold Time from Transmitter (Notes 1, 2)
0.3 − UI
t
EYE
Eye Width (Notes 1, 2)
− 0.6 UI
t
TOTALJIT
Data Total Jitter (pk-pk) @1e−9 (Notes 1, 2)
− 0.2 UI
t
CKJIT
Clock Period Jitter (RMS) (Note 2)
− 50 ps
t
CYCJIT
Clock Cycle-to-Cycle Jitter (RMS) (Note 2)
− 100 ps
t
R
Rise Time (20−80%) (Note 3)
150 ps 0.3 UI
t
F
Fall Time (20−80%) (Note 3)
150 ps 0.3 UI
D
CYC
Clock Duty Cycle (Note 2)
45 55 %
t
CHSKEW
Clock to Data Skew (Notes 1, 4)
−0.1 0.1 UI
t
PHYSKEW
PHY-to-PHY Skew (Notes 1, 5)
− 2.1 UI
t
DIFFSKEW
Mean Differential Skew (Note 6)
−100 100 ps
1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from the 0 V crossing point with the DLL off.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean V
CM
point. Note that differential skew also is related to the DVCM_AC spec which also must not be exceeded.
