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AR0330CM1C00SHAA0-DP2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
AR0330CM
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7
PIN DESCRIPTIONS
Table 5. PIN DESCRIPTIONS
Name
Type Description
RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default.
EXTCLK Input Master input clock, range 6−27 MHz.
OE_BAR Input Output enable (active LOW). Only available on bare die version.
TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame.
S
ADDR
Input Two-wire serial address select.
S
CLK
Input Two-wire serial clock input.
S
DATA
I/O Two-wire serial data I/O.
PIXCLK Output Pixel clock out. D
OUT
is valid on rising edge of this clock.
D
OUT
[11:0] Output Parallel pixel data output.
FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used.
FRAME_VALID Output Asserted when D
OUT
data is valid.
LINE_VALID Output Asserted when D
OUT
data is valid.
V
DD
Power Digital power.
V
DD
_IO Power IO supply power.
V
DD
_PLL Power PLL power supply. The MIPI power supply (V
DD
_MIPI) is tied to V
DD
_PLL in both packages.
D
GND
Power Digital GND.
V
AA
Power Analog power.
V
AA
_PIX Power Pixel power.
A
GND
Power Analog GND.
TEST Input Enable manufacturing test modes. Tie to D
GND
for normal sensor operation.
SHUTTER Output Control for external mechanical shutter. Can be left floating if not used.
SLVS0_P
Output HiSPi serial data, lane 0, differential P.
SLVS0_N
Output HiSPi serial data, lane 0, differential N.
SLVS1_P
Output HiSPi serial data, lane 1, differential P.
SLVS1_N
Output HiSPi serial data, lane 1, differential N.
SLVS2_P
Output HiSPi serial data, lane 2, differential P.
SLVS2_N
Output HiSPi serial data, lane 2, differential N.
SLVS3_P
Output HiSPi serial data, lane 3, differential P.
SLVS3_N
Output HiSPi serial data, lane 3, differential N.
SLVSC_P
Output HiSPi serial DDR clock differential P.
SLVSC_N
Output HiSPi serial DDR clock differential N.
DATA1_P Output MIPI serial data, lane 1, differential P.
DATA1_N Output MIPI serial data, lane 1, differential N.
DATA2_P Output MIPI serial data, lane 2, differential P.
DATA2_N Output MIPI serial data, lane 2, differential N.
DATA3_P Output MIPI serial data, lane 3, differential P.
DATA3_N Output MIPI serial data, lane 3, differential N.
DATA4_P Output MIPI serial data, lane 4, differential P.
DATA4_N Output MIPI serial data, lane 4, differential N.
AR0330CM
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8
Table 5. PIN DESCRIPTIONS (continued)
Name DescriptionType
CLK_P Output Output MIPI serial clock, differential P.
CLK_N Output Output MIPI serial clock, differential N.
V
DD
_HiSPi Power 1.8 V power port to HiSPi digital logic.
V
DD
_HiSPi_TX Power 0.4−0.8 V or 1.7−1.9 V. Refer to “HiSPi Power Supply Connections”.
V
AA
_HV_NPIX Power Power supply pin used to program the sensor OTPM (one-time programmable memory).
This pin should be open if OTPM is not used.
Table 6. CSP (HiSPi/MIPI) PACKAGE PINOUT
1 2 3 4 5 6 7 8
A
V
AA
V
AA
_HV_NPIX A
GND
A
GND
V
AA
V
DD
TEST D
GND
B
D
GND
NC V
AA
_PIX D
GND
V
DD
_IO TRIGGER RESET_BAR EXTCLK
C
V
DD
SHUTTER D
GND
SLVSC_P SLVS3_P SLVS3_N SLVS2_N SLVS2_P
D
S
ADDR
S
CLK
SDATA FLASH SLVSC_N SLVS1_P V
DD
_HiSPi_TX V
DD
_HiSPi
E
V
DD
_IO V
DD
_IO CLK_N CLK_P D
GND
SLVS1_N SLVS0_N SLVS0_P
F
D
GND
V
DD
_IO D
GND
D
GND
DATA4_P DATA_N DATA_P V
DD
_PLL
G
V
DD
_IO V
DD
D
GND
V
DD
_IO DATA4_N DATA3_N DATA2_N V
DD
H
D
GND
V
DD
_IO V
DD
_IO D
GND
V
DD
_PLL DATA3_P DATA2_P V
DD
_PLL
NOTE: NC = No Connection.
Figure 5. CLCC Package Pin Descriptions
DATA4_N
DATA4_P
DATA3_N
DATA3_P
CLK_N
CLK_P
DATA2_N
DATA2_P
DATA1_N
DATA1_P
V
DD
_PLL
D
GND
V
AA
_PIX
A
GND
V
AA
D
GND
EXTCLK
RESET_BAR
TRIGGER
SHUTTER
TEST
V
DD
V
DD
_IO
D
GND
V
AA
_HV_NPIX
NC
D
GND
V
DD
D
GND
S
ADDR
S
CLK
S
DATA
FLASH
V
DD
_IO
V
DD
D
GND
SLVS3_P
SLVS3_N
SLVS2_P
SLVS2_N
SLVSC_P
SLVSC_N
V
DD
_HiSPi
V
DD
_HiSPi_TX
SLVS1_P
SLVS1_N
SLVS0_P
SLVS0_N
4843 1 6
42
31
30 19
7
18
NOTE: Pins labeled NC (Not Connected) should be tied to ground.
AR0330CM
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9
SENSOR INITIALIZATION
Power-Up Sequence
The recommended power-up sequence for the AR0330CS
is shown in Figure 6. The available power supplies
(V
DD
_IO, V
DD
_PLL, V
DD
_MIPI, V
AA
, V
AA
_PIX) must
have the separation specified below.
1. Turn on V
DD
_PLL and V
DD
_MIPI power supplies.
2. After 100 ms, turn on V
AA
and V
AA
_PIX power
supply.
3. After 100 ms, turn on V
DD
power supply.
4. After 100 ms, turn on V
DD
_IO power supply.
5. After the last power supply is stable, enable
EXTCLK.
6. Assert RESET_BAR for at least 1 ms.
7. Wait 150,000 EXTCLK periods (for internal
initialization into software standby.
8. Write R0x3152 = 0xA114 to configure the internal
register initialization process.
9. Write R0x304A = 0x0070 to start the internal
register initialization process.
10. Wait 150,000 EXTCLK periods.
11. Configure PLL, output, and image settings to
desired values.
12. Wait 1ms for the PLL to lock.
13. Set streaming mode (R0x301A[2] = 1).
Figure 6. Power Up
EXTCLK
V
AA
_PIX
V
AA
(2.8)
V
DD
_IO (1.8/2.8)
V
DD
(1.8)
V
DD
_PLL,
V
DD
_MIPI (2.8)
t
0
t
1
t
2
t
3
t
4
t
5
t
X
Hard
Reset
Internal
Initialization
Software
Standby PLL Clock
Streaming
RESET_BAR
t
6
Internal
Initialization
R0x3152 = 0xA114
R0x304A = 0x0070
Notes:
1. A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers
a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above.
2. The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal initialization
sequence when the reset pin toggle from LOW to HIGH. This initialization sequence will run using the external input clock. Power on default
state is software standby state, need to apply two-wire serial commands to start streaming. Above power up sequence is a general power
up sequence. For different interface configurations, MIPI, and Parallel, some power rails are not needed. Those not needed power rails
should be ignored in the general power up sequence.
Table 7. POWER-UP SEQUENCE
Symbol
Definition Min Typ Max Unit
t
0
V
DD
_PLL, V
DD
_MIPI to V
AA
/V
AA
_PIX (Note 3) 0 100 –
ms
t
1
V
AA
/V
AA
_PIX to V
DD
0 100 –
ms
t
2
V
DD
to V
DD
_IO 0 100 –
ms
t
X
External Clock Settling Time (Note 1) – 30 – ms
t
3
Hard Reset (Note 2) 1 – – ms
t
4
Internal Initialization 150000 – – EXTCLKs
t
5
Internal Initialization 150000 – – EXTCLKs
t
6
PLL Lock Time 1 – – ms
1. External clock settling time is component-dependent, usually taking about 10–100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
3. It is critical that V
DD
_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that V
DD
_PLL is powered after other supplies then sensor may have functionality issues and will experience high
current draw on this supply.
4. V
DD
_MIPI is tied to V
DD
_PLL in the both the CLCC and CSP packages and must be powered to 2.8 V. The V
DD
_HiSPi and V
DD
_HiSPi_TX
supplies do not need to be turned on if the sensor is configured to use the MIPI or parallel interface.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

AR0330CM1C00SHAA0-DP2

Mfr. #:
Buy AR0330CM1C00SHAA0-DP2
Manufacturer:
ON Semiconductor
Description:
Image Sensors 3 MP 1/3 CIS Image Sensor
Lifecycle:
New from this manufacturer.
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