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AR0330CM1C00SHAA0-DP2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53
AR0330CM
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37
SLAVE MODE
The slave mode feature of the AR0330 supports triggering
the start of a frame readout from a VD signal that is supplied
from an external ASIC. The slave mode signal allows for
precise control of frame rate and register change updates.
The VD signal is input to the trigger pin. Both the GPI_EN
(R0x301A[8]) and the SLAVE_MODE (R0x30CE[4]) bits
must be set to “1” to enable the slave mode.
Figure 36. Slave Mode Active State and Vertical Blanking
Start of frame N
End of frame N
Start of frame N + 1
Time
Frame Valid
OB Rows (2, 4, or 8 rows)
Embedded Data Row (2 rows)
Active Data Rows
Blank Rows (2 rows)
Extra Vertical Blanking
(frame_length_lines − min_frame_length_lines)
VD Signal
Slave Mode Active State
Extra Delay (clocks)
The period between the
rising edge of the VD signal
and the slave mode ready
state is T
FRAME
= 16 clocks.
If the slave mode is disabled, the new frame will begin
after the extra delay period is finished.
The slave mode will react to the rising edge of the input
VD signal if it is in an active state. When the VD signal is
received, the sensor will begin the frame readout and the
slave mode will remain inactive for the period of one frame
time minus 16 clock periods (T
FRAME
− (16 / CLK_PIX)).
After this period, the slave mode will re-enter the active state
and will respond to the VD signal.
AR0330CM
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38
Figure 37. Slave Mode Example with Equal Integration and Frame Readout Periods
(The integration of the last row is therefore started before the end of the programmed integration for the first row)
Inactive Active
Row 0
Row N
Inactive Active
Rising
Edge
Rising
Edge
Row Readout
Programmed Integration
Slave Mode
Trigger
Rising edge of VD
signal triggers the start
of the frame readout.
Row Reset
(start of integration)
Frame
Valid
VD Signal
Rising
Edge
The Slave Mode will become “Active” after the last row period.
Both the row reset and row read operations will wait until the rising edge of the VD signal.
Row reset and read
operations begin
after the rising edge
of the VD signal.
Integration due to
Slave Mode Delay
The row shutter and read operations will stop when the
slave mode becomes active and is waiting for the VD signal.
The following should be considered when configuring the
sensor to use the slave mode:
1. The frame period (T
FRAME
) should be configured
to be less than the period of the input VD signal.
The sensor will disregard the input VD signal if it
appears before the frame readout is finished.
2. If the sensor integration time is configured to be
less than the frame period, then the sensor will not
have reset all of the sensor rows before it begins
waiting for the input VD signal. This error can be
minimized by configuring the frame period to be
as close as possible to the desired frame rate
(period between VD signals).
Figure 38. Slave Mode Example where the Integration Period is Half of the Frame Readout Period
(The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration caused
by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of 16.6ms while
the integration time is configured to 8.33 ms)
Inactive Active
Row0
Row N
Inactive Active
Rising
Edge
Rising
Edge
Slave Mode
Trigger
Frame
Valid
VD Signal
Rising
Edge
Reset operation is held during slave mode “Active” state.
Row reset and read
operations begin after
the rising edge of the
Vd signal.
8.33 ms
8.33 ms
Row Readout
Programmed Integration
Row Reset
(start of integration)
Integration due to
Slave Mode Delay
AR0330CM
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39
When the slave mode becomes active, the sensor will
pause both row read and row reset operations.
NOTE: The row integration period is defined as the
period from row reset to row read.
When the AR0330 is working in slave mode, the external
trigger signal VD must have accurately controlled timing to
avoid uneven exposure in the output image. The VD timing
control should make the slave mode “wait period” less than
32 pixel clocks.
To avoid uneven exposure, programmed integration time
cannot be larger than VD period. To increase integration
time more than current VD period, the AR0330 must be
configured to work at a lower frame rate and read out image
with new VD to match the new timing.
The period between slave mode pulses must also be
greater than the frame period. If the rising edge of the VD
pulse arrives while the slave mode is inactive, the VD pulse
will be ignored and will wait until the next VD pulse has
arrived.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P53

AR0330CM1C00SHAA0-DP2

Mfr. #:
Buy AR0330CM1C00SHAA0-DP2
Manufacturer:
ON Semiconductor
Description:
Image Sensors 3 MP 1/3 CIS Image Sensor
Lifecycle:
New from this manufacturer.
Delivery:
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