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853S006AGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ICS853S006AGI REVISION A NOVEMBER 15, 2011 1 ©2011 Integrated Device Technology, Inc.
DATA SHEET
Low Skew, 1-to-6, Differential-to-
2.5V, 3.3V LVPECL/ECL Fanout Buffer
ICS853S006I
General Description
The ICS853S006I is a low skew, high performance 1-to-6
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S006I is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S006I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Six differential 2.5V, 3.3V LVPECL/ECL outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
• Maximum output frequency: 2GHz
• Output skew: 50ps (max)
• Part-to-part skew: 230ps (max)
• Propagation delay: 550ps (max)
• LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
• ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PCLK
V
CC
Q2
nQ2
Q1
nQ1
Q0
nQ0
V
CC
n
PCLK
V
C
C
Q5
nQ
5
Q4
nQ
4
Q3
nQ
3
V
C
C
VE
E
VB
B
Q0
nQ
0
Q1
nQ
1
PCLK
n
PCLK
Pulldown
Pullup/Pulldown
V
BB
Q2
nQ
2
Q3
nQ
3
Q4
nQ
4
Q5
nQ
5
ICS853S006I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
Pin AssignmentBlock Diagram
ICS853S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S006AGI REVISION A NOVEMBER 15, 2011 2 ©2011 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 8, 13, 20 V
CC
Power Positive supply pin.
2, 3
nQ0, Q0
Output Differential output pair. LVPECL interface levels.
4, 5
nQ1, Q1
Output Differential output pair. LVPECL interface levels.
6, 7
nQ2, Q2
Output Differential output pair. LVPECL interface levels.
9 PCLK Input Pulldown Non-inverting differential LVPECL clock input.
10 nPCLK Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
11 V
BB
Output Bias voltage.
12 V
EE
Power Negative supply pin.
14, 15
nQ3, Q3
Output Differential output pair. LVPECL interface levels.
16, 17
nQ4, Q4
Output Differential output pair. LVPECL interface levels.
18, 19
nQ5, Q5
Output Differential output pair. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLDOWN
Input Pulldown Resistor 75 kΩ
R
VCC/2
Pullup/Pulldown Resistors 50 kΩ
ICS853S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S006AGI REVISION A NOVEMBER 15, 2011 3 ©2011 Integrated Device Technology, Inc.
Function Tables
Table 3. Clock Input Function Table
Note 1: Please refer to the Applications Information, “Wiring the Differential Input to Accept Single Ended Levels”.
Inputs Outputs
Input to Output Mode PolarityPCLK nPCLK Q0:Q5 nQ0:nQ5
0 1 LOW HIGH Differential to Differential Non-Inverting
1 0 HIGH LOW Differential to Differential Non-Inverting
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting
Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

853S006AGILF

Mfr. #:
Buy 853S006AGILF
Manufacturer:
IDT
Description:
Clock Buffer SMALL SIGE ARRAY
Lifecycle:
New from this manufacturer.
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