ICS853S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S006AGI REVISION A NOVEMBER 15, 2011 7 ©2011 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= 0; V
EE
= -2.375V to -3.465V or , V
CC
= 2.375V to 3.465V; V
EE
= 0V,
T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters are measured at f 1GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter
-40°C 25°C 85°C
UnitsMin Typ Max Min Typ Max Min Typ Max
f
OUT
Output Frequency 2 2 2 GHz
t
PD
Propagation Delay; NOTE 1 230 375 530 260 400 535 300 420 550 ps
tsk(o) Output Skew; NOTE 2, 4 21 50 22 50 23 50 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 230 230 230 ps
tjit
Buffer Additive Phase Jitter, RMS;
156.25MHz, Integration Range:
1kHz – 40MHz, refer to Additive
Phase Jitter Section
0.08 0.09 0.10 ps
t
R
/ t
F
Output Rise/Fall
Time
20% to 80% 55 136 240 55 140 240 55 150 240 ps
10% to 90% 65 210 400 65 210 400 65 230 400 ps
ICS853S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S006AGI REVISION A NOVEMBER 15, 2011 8 ©2011 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz band
at a specified offset from the fundamental frequency to the power
value of the fundamental. This ratio is expressed in decibels (dBm)
or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above.
The device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependent on the input source and
measurement equipment.
Measured using a Rhode & Schwarz SMA 100 as the input source.
Additive Phase Jitter @ 156.25MHz
1kHz to 40MHz = 0.09ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
ICS853S006I Data Sheet LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ICS853S006AGI REVISION A NOVEMBER 15, 2011 9 ©2011 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
Output Skew
Output Rise/Fall Time
2.5V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Propagation Delay
Output Rise/Fall Time
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.3V ± 0.165V
V
CC
V
EE
V
CMR
Cross Points
V
PP
nPCLK
PCLK
tsk(o)
nQx
Qx
nQy
Qy
20%
80%
80%
20%
t
R
t
F
V
SWIN
G
nQ0:nQ5
Q0:Q5
SCOPE
Qx
nQx
V
EE
V
CC
2V
-0.5V ± 0.125V
tsk(pp)
P
art 1
P
art 2
nQx
Qx
nQy
Qy
t
PD
nQ0:nQ5
Q0:Q5
nPCLK
PCLK
10%
90%
90%
10%
t
R
t
F
V
SWIN
G
nQ0:nQ5
Q0:Q5

853S006AGILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer SMALL SIGE ARRAY
Lifecycle:
New from this manufacturer.
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