REV. A
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may result from its use. No license is granted by implication or otherwise
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a
ADF4210/ADF4211/ADF4212/ADF4213
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Dual RF/IF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
IF
LOCK
DETECT
MUXOUT
ADF4210/ADF4211/
ADF4212/ADF4213
CP
RF
CP
IF
PHASE
COMPARATOR
OUTPUT
MUX
14-BIT IF
R-COUNTER
REF
IN
RF
PRESCALER
RF
IN
PHASE
COMPARATOR
14-BIT RF
R-COUNTER
12-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
V
DD
1V
DD
2V
P
1V
P
2
AGND
RF
DGND
RF
DGND
IF
AGND
IF
RF
LOCK
DETECT
SDOUT
DGND
IF
IF
PRESCALER
IF
IN
8-BIT IF
A-COUNTER
CHARGE
PUMP
IF CURRENT
SETTING
REFERENCE
RFCP3 RFCP2 RFCP1
R
SET
FL
O
SWITCH
FL
O
IF CURRENT
SETTING
IFCP3 IFCP2 IFCP1
REFERENCE
CHARGE
PUMP
R
SET
12-BIT IF
B-COUNTER
FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
P
) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5 V and can be powered down when not in use.
REV. A
–2–
ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS
1
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
DD
1, V
DD
2 V
P
1, V
P
2 6.0 V
; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; R
SET
= 2.7 k dBm to 50 ;
T
A
= T
MIN
to T
MAX
unless otherwise noted.)
P
arameter B Version B Chips
2
Unit Test Conditions/Comments
RF/IF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
) See Figure 3 for Input Circuit.
ADF4210 0.1/1.2 0.1/1.2 GHz min/max Use a square wave for frequencies lower than F
MIN
.
ADF4211 0.1/2.0 0.1/2.0 GHz min/max
ADF4212 0.15/2.7 0.15/2.7 GHz min/max
ADF4213 0.2/3.0 0.2/3.0 GHz min/max
RF Input Sensitivity –10/0 –10/0 dBm min/max
IF Input Frequency (IF
IN
)
ADF4210 60/550 60/550 MHz min/max
ADF4211 60/550 60/550 MHz min/max
ADF4212 0.06/1.0 0.06/1.0 GHz min/max
ADF4213 0.06/1.0 0.06/1.0 GHz min/max
IF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
165 165 MHz max
RF/IF CHARACTERISTICS (5 V)
RF Input Frequency (RF
IN
) See Figure 3 for Input Circuit.
ADF4210 0.18/1.2 0.18/1.2 GHz min/max Use a square wave for frequencies lower than F
MIN
.
ADF4211 0.18/2.0 0.18/2.0 GHz min/max
ADF4212 0.2/2.3 0.2/2.3 GHz min/max
ADF4213 0.2/2.5 0.2/2.5 GHz min/max
RF Input Sensitivity –5/0 –5/0 dBm min/max
IF Input Frequency (IF
IN
)
ADF4210 100/550 100/550 MHz min/max
ADF4211 100/550 100/550 MHz min/max
ADF4212 0.1/1.0 0.1/1.0 GHz min/max
ADF4213 0.1/1.0 0.1/1.0 GHz min/max
IF Input Sensitivity –5/0 –5/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
200 200 MHz max
REFIN CHARACTERISTICS See Figure 2 for Input Circuit.
REFIN Input Frequency 0/115 0/115 MHz min/max For F < 5 MHz, use dc-coupled square wave
(0 to V
DD
).
REFIN Input Sensitivity
4
–5/0 –5/0 dBm min/max AC-Coupled. When dc-coupled, 0 to V
DD
max
(CMOS-Compatible)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
5
55 55 MHz max
CHARGE PUMP
I
CP
Sink/Source Programmable: See Table V
High Value 5 5 mA typ With R
SET
= 2.7 k
Low Value 625 625 µA typ
Absolute Accuracy 3 3 % typ With R
SET
= 2.7 k
R
SET
Range 1.5/5.6 1.5/5.6 k, min/max
I
CP
Three-State Leakage Current 1 1 nA typ
Sink and Source Current Matching 2 2 % typ 0.5 V V
CP
V
P
– 0.5 V
I
CP
vs. V
CP
2 2 % typ 0.5 V V
CP
V
P
– 0.5 V
I
CP
vs. Temperature 2 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 0.8 × DV
DD
0.8 × DV
DD
V min
V
INL
, Input Low Voltage 0.2 × DV
DD
0.2 × DV
DD
V max
I
INH
/I
INL
, Input Current ± 1 ± 1 µA max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage DV
DD
– 0.4 DV
DD
– 0.4 V min I
OH
= 500 µA
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 µA
REV. A
–3–
ADF4210/ADF4211/ADF4212/ADF4213
Parameter B Version B Chips
2
Unit Test Conditions/Comments
POWER SUPPLIES
V
DD
1 2.7/5.5 2.7/5.5 V min/V max
V
DD
2V
DD
1V
DD
1
V
P
V
DD
1/6.0 V
DD
1/6.0 V min/V max V
DD
1, V
DD
2 V
DD
1, V
DD
2 6.0 V
I
DD
(RF + IF)
6
ADF4210 11.5 11.5 mA max 9.0 mA typical
ADF4211 15.0 15.0 mA max 11.0 mA typical
ADF4212 17.5 17.5 mA max 13.0 mA typical
ADF4213 20 20 mA max 15 mA typical
I
DD
(RF Only)
ADF4210 6.75 6.75 mA max 5.0 mA typical
ADF4211 10 10 mA max 7.0 mA typical
ADF4212 12.5 12.5 mA max 9.0 mA typical
ADF4213 15 15 mA max 11 mA typical
I
DD
(IF Only)
ADF4210 5.5 5.5 mA max 4.5 mA typical
ADF4211 5.5 5.5 mA max 4.5 mA typical
ADF4212 5.5 5.5 mA max 4.5 mA typical
ADF4213 5.5 5.5 mA max 4.5 mA typical
I
P
(I
P
1 + I
P
2) 1.0 1.0 mA max T
A
= 25°C, 0.55 mA typical
Low-Power Sleep Mode 1 1 µA typ
NOISE CHARACTERISTICS
ADF4213 Phase Noise Floor
7
–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency
Phase Noise Performance
8
@ VCO Output
ADF4210/ADF4211, IF: 540 MHz Output
9
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
ADF4212/ADF4213, IF: 900 MHz Output
10
–89 –89 dBc/Hz typ See Note 11
ADF4210/ADF4211, RF: 900 MHz Output
10
–89 –89 dBc/Hz typ See Note 11
ADF4212/ADF4213, RF: 900 MHz Output
10
–91 –91 dBc/Hz typ See Note 11
ADF4211/ADF4212, RF: 1750 MHz Output
12
–85 –85 dBc/Hz typ See Note 11
ADF4211/ADF4212, RF: 1750 MHz Output
13
–67 –67 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency
ADF4212/ADF4213, RF: 2400 MHz Output
14
–88 –88 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency
Spurious Signals
ADF4210/ADF4211, IF: 540 MHz Output
9
–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4212/ADF4213, IF: 900 MHz Output
10
–90/–94 –90/–94 dB typ See Note 11
ADF4210/ADF4211, RF: 900 MHz Output
10
–90/–94 –90/–94 dB typ See Note 11
ADF4212/ADF4213, RF: 900 MHz Output
10
–90/–94 –90/–94 dB typ See Note 11
ADF4211/ADF4212, RF: 1750 MHz Output
12
–80/–82 –80/–82 dB typ See Note 11
ADF4211/ADF4212, RF: 1750 MHz Output
13
–65/–70 –65/–70 dB typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency
ADF4212/ADF4213, RF: 2400 MHz Output
14
–80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels, T
A
= 25°C.
5
Guaranteed by design. Sample tested to ensure compliance.
6
V
DD
= 3 V; P = 16; RF
IN
= 900 MHz; IF
IN
= 540 MHz, T
A
= 25°C.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See
TPC 16.
8
The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
Same conditions as listed in Note 10.
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; Offset frequency = 1 kHz; f
RF
= 1960 MHz; N = 9800; Loop B/W = 20 kHz.
Specifications subject to change without notice.

ADF4212BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Dual Integer-N 0.5 GHz/3.0 GHz
Lifecycle:
New from this manufacturer.
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