REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–4–
DB0 (LSB)
(CONTROL BIT C1)
CLOCK
DATA
LE
LE
DB20
(MSB)
DB19 DB2
DB1
(CONTROL BIT C2)
t
6
t
5
t
1
t
2
t
3
t
4
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Limit at
T
MIN
to T
MAX
Parameter (B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK Set-Up Time
t
2
10 ns min DATA to CLOCK Hold Time
t
3
25 ns min CLOCK High Duration
t
4
25 ns min CLOCK Low Duration
t
5
10 ns min CLOCK to LE Set-Up Time
t
6
20 ns min LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
DD
1, V
DD
2 V
P
1, V
P
2
6 V 10%; AGND
RF
= DGND
RF
= AGND
IF
= DGND
IF
= 0 V; T
A
= T
MIN
to T
MAX
unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B,
IF
IN
A, IF
IN
B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θ
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θ
JA
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W
CSP θ
JA
(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model Temperature Range Package Description Package Option*
ADF4210BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4210BCP –40°C to +85°C Chip Scale Package CP-20
ADF4211BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4211BCP –40°C to +85°C Chip Scale Package CP-20
ADF4212BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4212BCP –40°C to +85°C Chip Scale Package CP-20
ADF4213BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4213BCP –40°C to +85°C Chip Scale Package CP-20
*Contact the factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–5–
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP Mnemonic Function
1V
DD
1 Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. V
DD
1 should have a value of between 2.7 V and 5.5 V. V
DD
1 must have
the same potential as V
DD
2.
2V
P
1 Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
1. In systems where
V
DD
1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
3CP
RF
Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.
4 DGND
RF
Ground Pin for the RF Digital Circuitry.
5RF
IN
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
6 AGND
RF
Ground Pin for the RF Analog Circuitry.
7FL
O
RF/IF Fastlock Mode.
8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
9 DGND
IF
Digital Ground for the IF Digital, Interface and Control Circuitry.
10 MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
14 R
SET
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
I
R
CP MAX
SET
=
13 5.
So, with R
SET
= 2.7 k, I
CP MAX
= 5 mA for both the RF and IF Charge Pumps.
15 AGND
IF
Ground Pin for the IF Analog Circuitry.
16 IF
IN
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
17 DGND
IF
Ground Pin for the IF Digital, Interface, and Control Circuitry.
18 CP
IF
Output from the IF Charge Pump. This is normally connected to a loop lter which drives the input
to an external VCO.
19 V
P
2 Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
2. In systems where
V
DD
2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
20 V
DD
2 Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. V
DD
2 should have a value of between 2.7 V and 5.5 V. V
DD
2
must have the same potential as V
DD
1.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA
CLK
MUXOUT
DGND
RF
RF
IN
AGND
RF
DGND
IF
REF
IN
FL
O
LE
R
SET
AGND
IF
V
DD
1
V
DD
2
V
P
2
IF
IN
DGND
IF
CP
IF
V
P
1
CP
RF
ADF4210/
ADF4211/
ADF4212/
ADF4213
CP-20
1
2
3
4
5
AGND
RF
FL
O
CP
RF
RF
IN
DGND
RF
V
DD
2
V
P
2
CP
IF
V
P
1
V
DD
1
20 19 18 17 16
15
14
13
12
11
DGND
IF
IF
IN
LE
R
SET
AGND
IF
6 7 8 9 10
REF
IN
DGND
IF
MUXOUT
DATA
CLK
TOP VIEW
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–6–
Typical Performance Characteristics
FREQUENCY S
11
REAL S
11
IMAG
50000000.0
150000000.0
250000000.0
350000000.0
450000000.0
550000000.0
650000000.0
750000000.0
850000000.0
950000000.0
1050000000.0
1150000000.0
1250000000.0
1350000000.0
1450000000.0
1550000000.0
1650000000.0
1750000000.0
1850000000.0
1950000000.0
2050000000.0
0.955683
0.956993
0.935463
0.919706
0.871631
0.838141
0.799005
0.749065
0.706770
0.671007
0.630673
0.584013
0.537311
0.505090
0.459446
0.381234
0.363150
0.330545
0.264232
0.242065
0.181238
–0.052267
–0.112191
–0.185212
–0.252576
–0.323799
–0.350455
–0.408344
–0.455840
–0.471011
–0.535268
–0.557699
–0.604256
–0.622297
–0.642019
–0.686409
–0.693908
–0.679602
–0.721812
–0.697386
–0.711716
–0.723232
2150000000.0
2250000000.0
2350000000.0
2450000000.0
2550000000.0
2650000000.0
2750000000.0
2850000000.0
2950000000.0
0.138086
0.102483
0.054916
0.018475
–0.019935
–0.054445
–0.083716
–0.129543
–0.154974
–0.699896
–0.704160
–0.696325
–0.669617
–0.668056
–0.666995
–0.634725
–0.615246
–0.610398
FREQUENCY S
11
REAL S
11
IMAG
TPC 1. S-Parameter Data for the ADF4213 RF Input
(Up to 3.0 GHz)
2kHz 1kHz 900MHz +1kHz +2kHz
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
91.2dBc/Hz
REFERENCE
LEVEL = 5.2dBm
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.6522
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
0.65 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
1kHz 10kHz 100kHz
TPC 3. ADF4213 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200
µ
s)
0
RF INPUT POWER dBm
30
20
10
0
T
A
= +25C
T
A
= 40C
35
25
5
15
RF INPUT FREQUENCY GHz
V
DD
= 3V
V
P
= 3V
123
T
A
= +85C
TPC 4. Input Sensitivity (ADF4213)
10dB/DIVISION R
L
= 40dBc/Hz RMS NOISE = 0.5421
100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
0.54 rms
PHASE NOISE dBc/Hz
90
80
70
60
50
40
100
110
120
130
140
1kHz 10kHz 100kHz
TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,
20 kHz, Typical Lock Time: 400
µ
s)
400kHz 200kHz
900MHz
200kHz 400kHz
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2 SECONDS
AVERAGES = 20
91.0dBc/Hz
REFERENCE
LEVEL = 5.7dBm
OUTPUT POWER dB
100
90
80
70
60
50
40
30
20
10
0
TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

ADF4212BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Dual Integer-N 0.5 GHz/3.0 GHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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