Operation M41T56
10/27 Doc ID 6104 Rev 9
2.2 Read mode
In this mode, the master reads the M41T56 slave after setting the slave address (see
Figure 7 on page 11 and Figure 8 on page 11). Following the WRITE mode control bit
(R/W
= 0) and the acknowledge bit, the word address A
n
is written to the on-chip address
pointer. Next the START condition and slave address are repeated, followed by the READ
mode control bit (R/W
= 1). At this point, the master transmitter becomes the master
receiver. The data byte which was addressed will be transmitted and the master receiver will
send an acknowledge bit to the slave transmitter. The address pointer is only incremented
on reception of an acknowledge bit. The M41T56 slave transmitter will now place the data
byte at address A
n
+ 1 on the bus. The master receiver reads and acknowledges the new
byte and the address pointer is incremented to A
n
+ 2. This cycle of reading consecutive
addresses will continue until the master receiver sends a STOP condition to the slave
transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T56
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer, see Figure 9 on page 11.
Table 2. AC characteristics
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= –40 to 85 °C; V
CC
= 4.5 to 5.5 V (except where noted).
Min Max Unit
f
SCL
SCL clock frequency 0 100 kHz
t
LOW
Clock low period 4.7 µs
t
HIGH
Clock high period 4 µs
t
R
SDA and SCL rise time 1 µs
t
F
SDA and SCL fall time 300 ns
t
HD:STA
START condition hold time
(after this period the first clock pulse is generated)
s
t
SU:STA
START condition setup time
(only relevant for a repeated start condition)
4.7 µs
t
SU:DAT
Data setup time 250 ns
t
HD:DAT
(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
edge of SCL.
Data hold time 0 µs
t
SU:STO
STOP condition setup time 4.7 µs
t
BUF
Time the bus must be free before a new
transmission can start
4.7 µs
M41T56 Operation
Doc ID 6104 Rev 9 11/27
Figure 7. Slave address location
Figure 8. Read mode sequence
Figure 9. Alternative read mode sequence
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
Operation M41T56
12/27 Doc ID 6104 Rev 9
2.3 Write mode
In this mode the master transmitter transmits to the M41T56 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'
(R/W
= 0) is placed on the bus and indicates to the addressed device that word address A
n
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T56
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 7 on page 11).
2.4 Data retention mode
With valid V
CC
applied, the M41T56 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T56 will automatically deselect,
write protecting itself when V
CC
falls between V
PFD
(max) and V
PFD
(min). This is
accomplished by internally inhibiting access to the clock registers and SRAM. When V
CC
falls below the battery backup switchover voltage (V
SO
), power input is switched from the
V
CC
pin to the battery and the clock registers and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up, when V
CC
returns to a nominal value,
write protection continues for t
REC
.
For a further more detailed review of battery lifetime calculations, please see application
note AN1012.
Figure 10. Write mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS

M41T56M6F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock Serial 512 (64x8)
Lifecycle:
New from this manufacturer.
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